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Volumn 36, Issue 11, 1989, Pages 2530-2536

High-Performance Salicide Shallow-Junction CMOS Devices for Submicrometer VLSI Application in Twin-Tub VI

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI--DESIGN; MICROELECTRONICS; SEMICONDUCTOR DEVICES, MOSFET;

EID: 0024768212     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.43677     Document Type: Article
Times cited : (23)

References (14)
  • 1
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    • Hillenius, S.J.1
  • 2
    • 0022999388 scopus 로고
    • 0.5 µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation
    • J.Y.-C. Sun, Y. Taur, R.H. Dennard, S.P. Klepner, and L.K. Wang, “0.5 µm-channel CMOS technology optimized for liquid-nitrogen-temperature operation,” in IEDM Tech. Dig., 1986, p. 236.
    • (1986) IEDM Tech. Dig. , pp. 236
    • Sun, J.Y.-C.1    Taur, Y.2    Dennard, R.H.3    Klepner, S.P.4    Wang, L.K.5
  • 3
    • 0024170162 scopus 로고
    • 0.5 micron CMOS for high performance at 3.3 V
    • R.A. Chapman et al., “0.5 micron CMOS for high performance at 3.3 V,” in IEDM Tech. Dig., 1988, p. 52.
    • (1988) IEDM Tech. Dig. , pp. 52
    • Chapman, R.A.1
  • 4
    • 84948599471 scopus 로고
    • U.S. Patent 4 554 726, Nov. 26
    • S.J. Hillenius and L.C. Panillo, U.S. Patent 4 554 726, Nov. 26, 1985.
    • (1985)
    • Hillenius, S.J.1    Panillo, L.C.2
  • 5
    • 0018321185 scopus 로고
    • Recrystallization of implanted amorphous silicon layers. I—Electrical properties of silicon implanted with BF2+ or Si+ + B+
    • M.Y. Tsai and B.G. Streetman, “Recrystallization of implanted amorphous silicon layers. I—Electrical properties of silicon implanted with BF2+ or Si+ + B+,” J. Appl. Phys., vol. 50, p. 183, 1979.
    • (1979) J. Appl. Phys. , vol.50 , pp. 183
    • Tsai, M.Y.1    Streetman, B.G.2
  • 6
    • 0020831863 scopus 로고
    • + implanted, pre-amorphized silicon
    • + implanted, pre-amorphized silicon,” IEEE Electron Device Lett., vol. EDL-4, p. 353, 1983.
    • (1983) IEEE Electron Device Lett. , vol.EDL-4 , pp. 353
    • Seidel, T.E.1
  • 7
    • 34250869424 scopus 로고
    • + dual-gate CMOS technology
    • + dual-gate CMOS technology,” IEEE Electron Device Lett., vol. 10, p. 192, 1989.
    • (1989) IEEE Electron Device Lett. , vol.10 , pp. 192
    • Lu, C.Y.1
  • 8
    • 0022060371 scopus 로고
    • The temperature dependence of threshold voltages in submicrometer CMOS
    • J.J. Tzou, C.C. Yao, R. Cheung, and H. Chan, “The temperature dependence of threshold voltages in submicrometer CMOS,” IEEE Electron Device Lett., vol. EDL-6, p. 250, 1985.
    • (1985) IEEE Electron Device Lett. , vol.EDL-6 , pp. 250
    • Tzou, J.J.1    Yao, C.C.2    Cheung, R.3    Chan, H.4
  • 9
    • 84948592865 scopus 로고
    • Sealed-interface poly-buffer LOCOS isolation technology
    • to be published
    • J.M. Sung and C.Y. Lu, “Sealed-interface poly-buffer LOCOS isolation technology,” J. Electrochem. Soc., 1989, to be published.
    • (1989) J. Electrochem. Soc.
    • Sung, J.M.1    Lu, C.Y.2
  • 11
    • 0024175126 scopus 로고
    • Contraints in p-channel device engineering for submicron CMOS technology
    • M.L. Chen et al., “Contraints in p-channel device engineering for submicron CMOS technology,” in IEDM Tech. Dig., 1988, p. 390.
    • (1988) IEDM Tech. Dig. , pp. 390
    • Chen, M.L.1
  • 12
    • 0022290102 scopus 로고
    • Gate material work function considerations for 0.5 micron CMOS
    • S.J. Hillenius and W.T. Lynch, “Gate material work function considerations for 0.5 micron CMOS,” in Proc. ICCD, 1985, p. 147.
    • (1985) Proc. ICCD , pp. 147
    • Hillenius, S.J.1    Lynch, W.T.2
  • 13
    • 0021640296 scopus 로고
    • +-polysilicon/silicide polysilicon/silicide gate for NMOS and PMOS devices
    • +-polysilicon/silicide polysilicon/silicide gate for NMOS and PMOS devices,” in IEDM Tech. Dig., 1984, p. 418.
    • (1984) IEDM Tech. Dig. , pp. 418
    • Parrillo, L.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.