Analysis and Modeling of On-Chip High-Voltage Generator Circuits for Use in EEPROM Circuits

IEEE Journal of Solid-State Circuits

Volumn 24, Issue 5, 1989, Pages 1372-1380

  Witters, Johan S ^a   Groeseneken, Guido ^a   Maes, Herman E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR--ELECTRIC POWER SUPPLIES; ELECTRONIC CIRCUITS, POWER SUPPLY; SEMICONDUCTOR DEVICES, MOS;

BODY EFFECT; CMOS INTEGRATED CIRCUITS; DICKSON VOLTAGE MULTIPLIER; EEPROM CIRCUITS; NONVOLATILE MEMORY DEGRADATION; VOLTAGE MULTIPLIERS;

DATA STORAGE, DIGITAL;

EID: 0024753848     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1989.572617     Document Type: Article

References (10)

1. D. Cioaca, T. Lin, A. Chan, L. Chen, and A. Mihnea, “A millioncycle CMOS 256K EEPROM,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 684-692, Oct 1987.
2. D. Oto et al., “High-voltage regulation and process considerations for high-density 5V-only EEPROM’s,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 532-538, Oct. 1983.
3. J. Dickson, On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976.
4. b. Gerber and J. Fellrath, “Low voltage single supply CMOS electrically erasable read-only memory,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1211-1216, July 1980.
5. E. K. Shelton, “Low-power EEPROM can be reprogrammed fast,” Electronics, vol. 53, pp. 89-92, July 1980.
6. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New YorK: Wiley, 1981.
7. N. D. Arora, Semi-empirical model for the threshold voltage of a double implanted MOSFET and its temperature dependence,” Solid-State Electron., vol. 30, pp. 559-569, May 1987.
8. G. Groeseneken and H. Maes, “A quantitative model for the conduction in oxides thermally grown from polycristalline silicon,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1028-1042, July 1986.
9. N. Mielke, A. Farion, and H.-C. Liou, “Reliability comparison of FLOTOX and textured polysilicon EEPROMs,” in Proc. Int. Rel. Phys. Symp., 1987, pp. 85-92.
10. D. Guterman, I. Rimawi, T. Chiu, R. Halvorson, and D. McElroy, “An electrically erasable nonvolatile memory cell using a floating gate structure,” IEEE Trans. Electron Devices, vol. ED-26, pp. 576–586, Apr. 1979.