An efficient on-chip deterministic test pattern generation scheme

Microprocessing and Microprogramming

Volumn 26, Issue 3, 1989, Pages 195-204

  Das, Aloke K ^a   Pal Chaudhuri, P ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Additive CA; AT2 costing; Cellular automata (CA); Group CA rule; On chip deterministic testing

Indexed keywords

AUTOMATA THEORY--APPLICATIONS; COMPUTER PROGRAMMING--ALGORITHMS; MATHEMATICAL TECHNIQUES--MATRIX ALGEBRA;

ALGORITHM REFINEMENT; CELLULAR AUTOMATA (CA); ON-CHIP DETERMINISTIC TEST PATTERN GENERATION; RELEVANT CYCLES GENERATION; TEST SET ALGORITHM; TESTING COSTS EVALUATION;

INTEGRATED CIRCUITS, VLSI;

EID: 0024750008     PISSN: 01656074     EISSN: None     Source Type: Journal    
DOI: 10.1016/0165-6074(89)90254-8     Document Type: Article

References (10)

1. Self-testing of multi-chip logic modules
2. Built-in logic block observation techniques
3. CALBO — Cellular Automaton Logic Block Observation
4. Covering a set of test patterns by a cellular automaton
5. Group properties of cellular automata and VLSI applications
6. An efficient characterization of cellular automata
7. Cellular automata used for test pattern generation
8. Algebric properties of cellular automata
9. Statistical mechanics of cellular automata
10. Cellular automata mechanics