-
1
-
-
0018024380
-
An experimental 64-bit decoded Josephson NDRO random access memory
-
Oct.
-
W. H. Henkels and H. H. Zape, “An experimental 64-bit decoded Josephson NDRO random access memory,'’ IEEE J. Solid-State Circuits, vol. SC-13, no. 5, pp. 591–600, Oct. 1978.
-
(1978)
IEEE J. Solid-State Circuits
, vol.SC-13
, Issue.5
, pp. 591-600
-
-
Henkels, W.H.1
Zape, H.H.2
-
2
-
-
0018700056
-
Fundamental criteria for the design of high-per-formance readout random access memory cells and experimental confirmation
-
Dec.
-
W. H. Henkels, “Fundamental criteria for the design of high-per-formance readout random access memory cells and experimental confirmation,” J. Appl. Phys., vol. 50, no. 12, pp. 8143–8168, Dec. 1979.
-
(1979)
J. Appl. Phys.
, vol.50
, Issue.12
, pp. 8143-8168
-
-
Henkels, W.H.1
-
3
-
-
33645548216
-
Basic design of a Josephson technology cache memory
-
Mar.
-
S. M. Paris, W. H. Henkels, E. A. Valsamakis, and H. H. Zappe, “Basic design of a Josephson technology cache memory,” IBM J. Res. Develop., vol. 24, no. 2, pp. 143–154, Mar. 1980.
-
(1980)
IBM J. Res. Develop.
, vol.24
, Issue.2
, pp. 143-154
-
-
Paris, S.M.1
Henkels, W.H.2
Valsamakis, E.A.3
Zappe, H.H.4
-
4
-
-
0020747870
-
An experimental nanosecond Josephson IK RAM using 5-μm Pb-alloy technology
-
May
-
M. Yamamoto et al., “An experimental nanosecond Josephson IK RAM using 5-μm Pb-alloy technology,” IEEE Electron Device Lett., vol. EDL-4, no. 5, pp. 150–152, May 1983.
-
(1983)
IEEE Electron Device Lett.
, vol.EDL-4
, Issue.5
, pp. 150-152
-
-
Yamamoto, M.1
-
5
-
-
0024055794
-
AC- and DC-powered subnanosecond 1-kbit Josephson cache memory design
-
Aug.
-
Y. Wada, M. Hidaka, S. Nagasawa, and I. Ishida, “AC- and DC-powered subnanosecond 1-kbit Josephson cache memory design,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 923–932, Aug. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, Issue.4
, pp. 923-932
-
-
Wada, Y.1
Hidaka, M.2
Nagasawa, S.3
Ishida, I.4
-
6
-
-
0023436118
-
280-ps 6-bit RCJL decoder using high-drivability and unit circuit for a 1-kbit Josephson cache memory
-
Oct.
-
Y. Wada, S. Nagasawa, and I. Ishida, “280-ps 6-bit RCJL decoder using high-drivability and unit circuit for a 1-kbit Josephson cache memory,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 892–898, Oct. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SC-22
, Issue.5
, pp. 892-898
-
-
Wada, Y.1
Nagasawa, S.2
Ishida, I.3
-
7
-
-
0022077548
-
An AC-powered experimental memory circuit with a resistively loaded sense circuit
-
June
-
M. Hidaka, J. Sone, I. Ishida, and Y. Wada, “An AC-powered experimental memory circuit with a resistively loaded sense circuit,” IEEE Electron Device Lett., vol. EDL-6, no. 6, pp. 267–269, June 1985.
-
(1985)
IEEE Electron Device Lett.
, vol.EDL-6
, Issue.6
, pp. 267-269
-
-
Hidaka, M.1
Sone, J.2
Ishida, I.3
Wada, Y.4
-
8
-
-
0024627888
-
Nb multilayer planarization technology for a subnanosecond Josephson IK-bit RAM
-
Mar.
-
S. Nagasawa et al., “Nb multilayer planarization technology for a subnanosecond Josephson IK-bit RAM,” IEEE Trans. Magn., vol. 25, no. 2, pp. 777–782, Mar. 1989.
-
(1989)
IEEE Trans. Magn.
, vol.25
, Issue.2
, pp. 777-782
-
-
Nagasawa, S.1
-
9
-
-
0346989455
-
Resister coupled Josephson logic
-
Apr.
-
J. Sone, T. Yoshida, and H. Abe, “Resister coupled Josephson logic,” Appl. Phys. Lett., vol. 40, no. 8, pp. 741–744, Apr. 1982.
-
(1982)
Appl. Phys. Lett.
, vol.40
, Issue.8
, pp. 741-744
-
-
Sone, J.1
Yoshida, T.2
Abe, H.3
-
10
-
-
0023997964
-
A uniform polymer coating technique for an etch back planarization process using low molecular polymers
-
H. Gokan, M.Mukainaru, and N. Endo, “A uniform polymer coating technique for an etch back planarization process using low molecular polymers,” J. Electrochem. Soc., vol. 135, pp. 1019–1020, 1988.
-
(1988)
J. Electrochem. Soc.
, vol.135
, pp. 1019-1020
-
-
Gokan, H.1
Mukainaru, M.2
Endo, N.3
-
11
-
-
0024055402
-
Planarization technology for Josephson integrated circuits
-
Aug.
-
S. Nagasawa, H. Tsuge, and Y. Wada, “Planarization technology for Josephson integrated circuits,” IEEE Electron Device Lett., vol. 9, no, 8, pp. 414–416, Aug. 1988.
-
(1988)
IEEE Electron Device Lett.
, vol.9
, pp. 414-416
-
-
Nagasawa, S.1
Tsuge, H.2
Wada, Y.3
-
12
-
-
0023562028
-
Lift-off planarization process for Josephson IC multilevel interconnections
-
I. Ishida, S. Tahara, Y. Ajisawa, and Y. Wada, “Lift-off planarization process for Josephson IC multilevel interconnections,” in Proc, 19th Conf. Solid State Devices and Mater. (Tokyo, Japan), 1987, pp. 433–446.
-
(1987)
Proc, 19th Conf. Solid State Devices and Mater. (Tokyo, Japan)
, pp. 433-446
-
-
Ishida, I.1
Tahara, S.2
Ajisawa, Y.3
Wada, Y.4
-
13
-
-
0024144015
-
Thermal stability of Nb/A10x/Nb Josephson junction
-
M. Hidaka, H. Tsuge, and Y. Wada, “Thermal stability of Nb/A10 x/Nb Josephson junction,” Advances Cryogenic Eng. Mater., vol. ‘34, pp. 765–772, 1988.
-
(1988)
Advances Cryogenic Eng. Mater.
, vol.34
, pp. 765-772
-
-
Hidaka, M.1
Tsuge, H.2
Wada, Y.3
-
14
-
-
0019068298
-
Memory-cell design in Josephson technology
-
Oct.
-
H. H. Zappe, “Memory-cell design in Josephson technology,” IEEE Trans. Electron Devices, vol. ED-27, no. 10, pp. 1870–1882, Oct. 1980.
-
(1980)
IEEE Trans. Electron Devices
, vol.ED-27
, Issue.10
, pp. 1870-1882
-
-
Zappe, H.H.1
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