Vertical scalability of forward delay times in bipolar transistors

IEEE Transactions on Electron Devices

Volumn 36, Issue 9, 1989, Pages 1841-1844

  Castaner L ^a   Ashburn, P ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL; MATHEMATICAL TECHNIQUES--INTEGRAL EQUATIONS;

BIPOLAR TRANSISTOR DELAY TIME; BIPOLAR TRANSISTOR VERTICAL DIMENSIONS; FORWARD DELAY TIMES;

TRANSISTORS, BIPOLAR;

EID: 0024738907     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.34251     Document Type: Article

References (16)

1. L. Castaner, P. Ashbum, L. Prat, and G. R. Wolstenholme, “The asymptotes of the base current in bipolar devices,” IEEE Trans. Electron Devices, vol. 35, pp. 1902–1908, 1988.
2. S. N. Mohammad, “Emitter efficiency, transit times and current gain of bipolar transistors,” Solid-State Electron., vol. 30, no. 7, pp. 685–692, 1987.
3. + silicon emitters,” Solid-State Electron., vol. 29, no. 12, pp. 1243–1251, 1986.
4. P. Ashbum, A. A. Rezazadeh, E. F. Chor, and A. Brunnschweiler, “Comparison of silicon bipolar and GaAs/GaAlAs heterojunction technologies for high speed ECL circuits,” in Proc. Bipolar Circuits Technol. Meeting, 1987, pp. 61–64.
5. D. J. Roulston, BIPOLE User's Manual, Univ. of Waterloo, Ontario, Canada, 1985.
6. H. Schaber, J. Bieger, B. Benna, and T. E. Meister, “Vertical scaling considerations for polysilicon-emitter bipolar transistors” in Proc. 17th ESSDERC, 1987, pp. 365–368.
7. J. del Alamo, S. Swirhun, and R. M. Swanson “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” in IEDM Tech. Dig., 1985, pp. 290–293.
8. S. E. Swirhun, Y. H. Kwark, and R. M. Swanson. “Measurement of electron lifetime, electron mobility and bandgap narrowing in heavily doped p-type silicon,” in IEDM Tech. Dig., 1986, pp. 24–27.
9. J. del Alamo, S. Swirhun, and R. M. Swanson, “Measuring and modeling minority carrier transport in heavily doped silicon,” Solid-State Electron., vol. 28, pp. 47–54, 1985.
10. J. Wagner and J. del Alamo, “Band-gap narrowing in heavily doped silicon: A comparison of optical and electrical data,” J. Appl. Phys., vol. 63, pp. 425–429, 1987.
11. G. R. Wolstenholme, N. Jorgensen, P. Ashbum, and G. R. Booker, “An investigation of the thermal stability of the interfacial oxide in polycristalline silicon emitter bipolar transistors by comparing device results with high resolution electron microscopy observations,” J. Appl. Phys., vol. 61, pp. 225–233, 1986.
12. J. S. Park, A. Neugroschel, and F. A. Lindholm, “Systematic analytical solutions for minority-carrier transport in semiconductors with position-dependent composition, with application to heavily doped silicon,” IEEE Trans. Electron Devices, vol. ED-32, pp. 240–249, 1986.
13. J. del Alamo and R. M. Swanson, “The physics and modeling of heavily doped emitters,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1878–1888, 1984.
14. M. A. Shibib, F. A. Lindholm, and F. Therez, “Heavily doped transparent-emitter regions in junction solar cells, diodes and transistors,” IEEE Trans. Electron Devices, vol. ED-26, pp. 959–965, June 1979.
15. S. Y. Yung and D. E. Burk, “Informed device design and gain-speed tradeoff for self aligned polysilicon emitter transistors,” Solid-State Electron., vol. 31, pp. 1139–1150, 1988.
16. Z. Yu, B. Riccò, and R. W. Dutton, “A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 773–784, 1984.