Three-Dimensional Effects in Dynamically Triggered CMOS Latchup

IEEE Transactions on Electron Devices

Volumn 36, Issue 9, 1989, Pages 1683-1690

  Fiegna, Claudio ^a   Selmi, Luca ^a   Ricco, Bruno ^a   Sangiorgi, Enrico ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORKS, LUMPED PARAMETER;

3D LATCHUP PHENOMENON; CMOS LATCHUP; LATCHUP LUMPED ELEMENT MODEL;

SEMICONDUCTOR DEVICES, MOS;

EID: 0024732880     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.34230     Document Type: Article

References (9)

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2. L. Selmi, E. Sangiorgi, G. Crisenza, D. Re, and B. Riccò, “Hysteresis cycle in the latch-up characteristics of wide CMOS structures,” IEEE Electron Device Lett., vol. 9, p. 214, 1988.
3. A. G. Lewis, R. A. Martin, T. Y. Huang, and J. Y. Chen, “Three dimensional effects in CMOS latch-up,” in IEDM Tech. Dig., 1986, p. 248.
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5. R. R. Troutman and H. P. Zappe, “Layout and bias considerations for preventing transiently triggered latch-up in CMOS,” IEEE Trans Electron Devices, vol. ED-31, p. 315, 1984.
6. I. Getreu, Modeling the Bipolar Transistor. New York: Elsevier North-Holland, 1976.
7. R. R. Troutman, Latchup in CMOS Technology. Boston: Kluwer Academic, 1986, pp. 140-145, 152-153.
8. D. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Stanford Univ., Stanford, CA, Tech. Rep. G-201-9, 1980.
9. R. S. Muller, and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed. New York: Wiley, 1986.