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Volumn 6, Issue 3, 1989, Pages 8-34

Accuracy vs. speed in placement

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS, DIGITAL - PARALLEL PROCESSING; INTEGRATED CIRCUITS - COMPUTER AIDED DESIGN; MATHEMATICAL TECHNIQUES - COMBINATORIAL MATHEMATICS; SYSTEMS SCIENCE AND CYBERNETICS - HEURISTIC PROGRAMMING;

EID: 0024686286     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.32410     Document Type: Article
Times cited : (19)

References (22)
  • 1
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    • Optimization by Simulated Annealing
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    • S. Kirkpatrick, C. Gelatt, Jr., and M. Vecchi, “Optimization by Simulated Annealing,” Science, Vol. 220, No. 459, May 1983, pp. 45-54.
    • (1983) Science , vol.220 , Issue.459 , pp. 45-54
    • Kirkpatrick, S.1    Gelatt, C.2    Vecchi, M.3
  • 3
    • 0021541068 scopus 로고
    • Concepts of Scale in Simulated Annealing
    • S. White, “Concepts of Scale in Simulated Annealing,” Proc. Inf'l Conf. on Computer Design, 1984, pp. 646-651.
    • (1984) Proc. Inf'l Conf. on Computer Design , pp. 646-651
    • White, S.1
  • 4
    • 0021404023 scopus 로고
    • The TimberWolf Placement and Routing Package
    • Apr.
    • C. Sechen and A. Sangiovanni-Vincentelli, ‘The TimberWolf Placement and Routing Package,” IEEEJ. Solid-State Circuits, Vol. SC-20, No. 2, Apr. 1985, pp. 510-522.
    • (1985) IEEEJ. Solid-State Circuits , vol.SC-20 , Issue.2 , pp. 510-522
    • Sechen, C.1    Sangiovanni-Vincentelli, A.2
  • 5
    • 0023383256 scopus 로고
    • Placement by Simulated Annealing on a Multiprocessor
    • July
    • S. Kravitz and R. Ruttenbar, “Placement by Simulated Annealing on a Multiprocessor,” IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 4, July 1987, pp. 534-549.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , Issue.4 , pp. 534-549
    • Kravitz, S.1    Ruttenbar, R.2
  • 6
    • 0022953950 scopus 로고
    • Fast, High Quality VLSI Placement on an MIMD Multiprocessor
    • J. Rose et al., “Fast, High Quality VLSI Placement on an MIMD Multiprocessor,” Proc. Inti Conf. on Computer-Aided Design, 1986, pp. 42-45.
    • (1986) Proc. Inti Conf. on Computer-Aided Design , pp. 42-45
    • Rose, J.1
  • 7
    • 0023978575 scopus 로고
    • Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing
    • Mar.
    • J. Rose. W. Snelgrove, and Z. Vranesic, “Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing,” IEEE Trans. Computer-Aided Design, Vol. CAD-7, No. 3, Mar. 1988, pp. 387-396.
    • (1988) IEEE Trans. Computer-Aided Design , vol.CAD-7 , Issue.3 , pp. 387-396
    • Rose, J.1    Snelgrove, W.2    Vranesic, Z.3
  • 10
    • 0001157226 scopus 로고
    • A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells
    • Sept.
    • A. Casotto, F. Romeo, and A. Sangiovanni-Vincentelli, “A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells,” IEEE Trans. Computer-Aided Design, Vol. CAD-6, No. 5, Sept. 1987, pp. 838-847.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , Issue.5 , pp. 838-847
    • Casotto, A.1    Romeo, F.2    Sangiovanni-Vincentelli, A.3
  • 12
    • 0023435343 scopus 로고
    • Multipurpose Parallelism for VLSI CAD on the RP3
    • Oct.
    • F. Darema, and G. Pfister, “Multipurpose Parallelism for VLSI CAD on the RP3,” IEEE Design & Test of Computers, Oct. 1987, pp. 19-27.
    • (1987) IEEE Design & Test of Computers , pp. 19-27
    • Darema, F.1    Pfister, G.2
  • 13
    • 0023593851 scopus 로고
    • Floorplanning by Annealing on a Hypercube Multiprocessor
    • IEEE, Nov.
    • R. Jayaraman and R. Rutenbar, “Floorplanning by Annealing on a Hypercube Multiprocessor,” Int'l  Conf. on Computer-Aided Design, IEEE, Nov. 1987, pp. 346-349.
    • (1987) Int'l  Conf. on Computer-Aided Design , pp. 346-349
    • Jayaraman, R.1    Rutenbar, R.2
  • 15
    • 0021793126 scopus 로고
    • The Cosmic Cube
    • Jan.
    • C. Seitz, ‘The Cosmic Cube,” Comm ACM, Vol. 28, No.1, Jan. 1985, pp. 22-33.
    • (1985) Comm ACM , vol.28 , Issue.1 , pp. 22-33
    • Seitz, C.1
  • 17
    • 0023592676 scopus 로고
    • Simulated Annealing-Based Circuit Placement Algorithm on the Connection Machine System
    • C-P. Wong and R-D. Fiebrich, “Simulated Annealing-Based Circuit Placement Algorithm on the Connection Machine System,” Proc. Int'l  Conf. on Computer Design, 1987, pp. 78-82. 18. W. Hillis, The Connection Machine, MIT Press, Cambridge, Mass., 1985.
    • (1985) Proc. Int'l  Conf. on Computer Design , pp. 78-82
    • Wong, C.-P.1    Fiebrich, R.-D.2
  • 20
    • 0023012985 scopus 로고
    • A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer
    • P. Banneijee and M. Jones, “A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer,” Proc. Inf'l Conf. on Computer-Aided Design, 1986, pp. 34-37.
    • (1986) Proc. Inf'l Conf. on Computer-Aided Design , pp. 34-37
    • Banneijee, P.1    Jones, M.2
  • 21
    • 0023211421 scopus 로고
    • Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube
    • M. Jones and P. Banneijee, “Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube,” Proc. Design Automation Conf. 1987, pp. 807-813.
    • (1987) Proc. Design Automation Conf. , pp. 807-813
    • Jones, M.1    Banneijee, P.2
  • 22
    • 0023590067 scopus 로고
    • An Improved Simulated Annealing Algorithm for Standard Cell Placement.
    • M. Jones and P. Banneijee, “An Improved Simulated Annealing Algorithm for Standard Cell Placement.,” Proc. Int'l Conf. on Computer Design, 1987, pp. 83-86.
    • (1987) Proc. Int'l Conf. on Computer Design , pp. 83-86
    • Jones, M.1    Banneijee, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.