Internal Thermal Resistance of a Multi-Chip Packaging Design for VLSI Based Systems

IEEE Transactions on Components, Hybrids, and Manufacturing Technology

Volumn 12, Issue 2, 1989, Pages 163-169

  Lee, Y C ^a   Ghaffari, H T ^a   Segelken, John M ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONICS PACKAGING--COOLING; HEAT SINKS; HEAT TRANSFER; SOLDERING;

ADVANCED VLSI PACKAGING; FLIP-CHIP SOLDERING; MULTICHIP PACKAGING; SILICON SUBSTRATE; SOLDER BUMPS;

INTEGRATED CIRCUITS, VLSI;

EID: 0024685478     PISSN: 01486411     EISSN: None     Source Type: Journal    
DOI: 10.1109/33.31420     Document Type: Article

References (5)

1. C. J. Bartlett, J. M. Segelken, and N. A. Teneketges, “Multi-chip packaging design for VLSI-based systems,” in ECC Conf. Proc, May 1987.
2. H. J. Levinstein, C. J. Bartlett, and W. J. Bertram, Jr., “Multi-chip packaging technology for VLSI-based systems,” in ISSCC Conf. Proc, Feb. 1987.
3. A. C. Adams, R. S. Bentson, W. J. Bertram, H. J. Levinstein, W. Q. McKnight, J. J. Rubin, and B. A. terHaar, “High density interconnect for advanced VLSI packaging,” Proc. Electochem. Soc, May 1987.
4. A. Bar-Cohen, “Thermal management of air and liquid-cooled multi-chip modules,” presented at the ASME Nat. Heat Transfer Conf., Denver, CO, 1985.
5. S. V. Patankar, Numerical Heat Transfer and Fluid Flow. New York, NY: Hemisphere Pub., 1980.