The Influence of Boundary Locations on Wiring Capacitance Simulation

IEEE Transactions on Electron Devices

Volumn 36, Issue 6, 1989, Pages 1171-1174

  Shigyo, Naoyuki ^a   Fukuda, Sanae ^a   Kato, Koichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION;

BOUNDARY LOCATIONS; NEUMANN BOUNDARY CONDITION; WIRING CAPACITANCE;

INTEGRATED CIRCUITS, VLSI;

EID: 0024682064     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.24364     Document Type: Article

References (9)

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9. Y. Nakagome et al., “The impact of data-line interference noise on DRAM scaling,” IEEEJ. Solid-State Circuits, vol. 23, pp. 1120–1127, 1988.