Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time

IEEE Journal of Solid-State Circuits

Volumn 24, Issue 3, 1989, Pages 558-561

  Rothermel, Albrecht ^a   Hosticka, Bedrich J ^a   TrÖster, Gerhard ^b   Arndt, Juergen ^b  

^a FRAUNHOFER INSTITUTE FOR MICROELECTRONIC CIRCUITS AND SYSTEMS   (Germany)

^b Telefunken Electronic GmbH ^*  (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS--DESIGN; SEMICONDUCTOR DEVICES, MOS;

LATENCY TIME; LAYOUT TECHNIQUES; PROPAGATION DELAY; TRANSMISSION CONDITIONAL SUM ADDERS;

COMPUTERS, DIGITAL;

EID: 0024681856     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.32007     Document Type: Article

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