MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Dai, Zhi jian ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LOGIC DESIGN; SEMICONDUCTOR DEVICES, MOS;

LOGIC STAGES; MULTISTAGE MOS CIRCUITS; SOFTWARE PACKAGE MOSIZ; TIMING ASSIGNMENT METHOD; TRANSISTOR SIZING ALGORITHM;

COMPUTER PROGRAMMING;

EID: 0024665705     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)