Process Integration and Device Performance of a Submicrometer BiCMOS with 16-GHz ft Double Poly-Bipolar Devices

IEEE Transactions on Electron Devices

Volumn 36, Issue 5, 1989, Pages 890-896

  Yamaguchi, Tadanori ^a   Yuzuriha, Todd H ^a  

^a TEKTRONIX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS, EMITTER COUPLED; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES, MOSFET; TRANSISTORS, BIPOLAR;

BICMOS DEVICES; CMOS CIRCUITS;

SEMICONDUCTOR DEVICES;

EID: 0024664156     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.299670     Document Type: Article

References (10)

1. Y. Nishino et al., “0.45 ns 7 K Hi-BiCMOS gate array with configurable 3-port 4.6 K SRAM,” in Proc. C1CC, May 1987, p. 203.
2. N. Tamba et al., “An 8 ns 256 K BiCMOS RAM,” in ISSCC Tech. Dig., Feb. 1988, p. 184.
3. R. A. Kertis, D. D. Smith, and T. L. Bowman, “A 12 ns 256 K BiCMOS SRAM,” in ISSCC Tech. Dig., Feb. 1988, p. 186.
4. H. V. Tran et al., “An 8 ns buttery backup submicron BiCMOS 256 K ECL RAM,” in ISSCC Tech. Dig., Feb. 1988, p. 188.
5. R. Hori et al., “An experimental 35 ns 1 Mb BiCMOS DRAM,” in ISSCC Tech. Dig., Feb. 1987, p. 280.
6. T. Hotta et al., “CMOS/bipolar circuits for 60-MHz digital processing,” IEEE J. Solid-State Circuits, vol. SC-21, p. 808, Oct. 1986.
7. T. Hotta et al., “1.3-μn CMOS/bipolar standard cell library for VLSI computers,” IEEE J. Solid-State Circuits, vol. SC-23, p. 500, Apr. 1988.
8. T. Yamaguchi et al., “Process and device performance of a high-speed double poly-Si bipolar technology using bofosenic-poly process with coupling-base implant,” IEEE Trans. Electron Devices, vol. 35, p. 1247, Aug. 1988.
9. H. Momose, K. M. Cham, C. I. Drowley, H. R. Grinolds, and H. S. Fu, “0.5 micron BiCMOS technology,” in IEDM Tech. Dig., Dec. 1987, p. 838.
10. E. W. Greeneich and K. L. McLaughlin, “Analysis and characterization of BiCMOS for high-speed digital logic,” IEEE J. Solid-State Circuits, vol. 23, p. 558, Apr. 1988.