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Volumn 24, Issue 2, 1989, Pages 358-369

Ultrafast Compact 32-bit CMOS Adders in Multiple-Output Domino Logic

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LOGIC DEVICES--GATES; SEMICONDUCTOR DEVICES, MOS;

EID: 0024647831     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.18596     Document Type: Article
Times cited : (65)

References (22)
  • 2
    • 0022859749 scopus 로고
    • Microprocessor technology trends
    • Dec
    • G. J. Myers et al., “Microprocessor technology trends,” Proc. IEEE, vol. 74, pp. 1605–1622, Dec. 1986.
    • (1986) Proc. IEEE , vol.74 , pp. 1605-1622
    • Myers, G.J.1
  • 3
    • 0024131555 scopus 로고
    • A 3.1 ns 32b CMOS adder in multiple output domino logic
    • I. S. Hwang and A. L. Fisher, “A 3.1 ns 32b CMOS adder in multiple output domino logic,” in ISSCC Dig. Tech. Papers, 1988, pp. 140–141.
    • (1988) ISSCC Dig. Tech. Papers , pp. 140-141
    • Hwang, I.S.1    Fisher, A.L.2
  • 5
    • 84869409300 scopus 로고
    • A high-speed dynamically reconfigurable 32-bit CMOS adder
    • I. S. Hwang and P. S. Magarshack, “A high-speed dynamically reconfigurable 32-bit CMOS adder,” in Proc. CICC, 1988, pp. 17.5.1-17.5.6.
    • (1988) Proc. CICC , pp. 17.5.1-17.5.6
    • Hwang, I.S.1    Magarshack, P.S.2
  • 6
    • 0001834707 scopus 로고
    • Cascoded voltage switch logic: A differential CMOS logic family
    • L. G. Heller et al., “Cascoded voltage switch logic: A differential CMOS logic family,” in 1SSCC Dig. Tech. Papers, 1984, pp. 16–17.
    • (1984) 1SSCC Dig. Tech. Papers , pp. 16-17
    • Heller, L.G.1
  • 7
    • 84864706535 scopus 로고
    • Differential split-level CMOS logic for subnanosecond speeds
    • Oct
    • L. C. M. G. Pfennings et al., “Differential split-level CMOS logic for subnanosecond speeds,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1050–1055, Oct. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 1050-1055
    • Pfennings, L.C.M.G.1
  • 8
    • 0021411604 scopus 로고
    • Dynamic logic CMOS circuits
    • Apr
    • V. Friedman and S. Liu, “Dynamic logic CMOS circuits,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 263–266, Apr. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , pp. 263-266
    • Friedman, V.1    Liu, S.2
  • 10
    • 0020776123 scopus 로고
    • NORA: A racefree dynamic CMOS technique for pipelined logic structures
    • June
    • N. F. Goncalves and H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State State Circuits, vol. SC-18, pp. 261–266, June 1983.
    • (1983) IEEE J. Solid-State State Circuits , vol.SC-18 , pp. 261-266
    • Goncalves, N.F.1    De Man, H.J.2
  • 14
    • 0023291971 scopus 로고
    • The analysis and design of CMOS multidrain logic and stacked multidrain logic
    • Feb
    • C.-Y. Wu, J.-S. Wang, and M.-K. Tsai, “The analysis and design of CMOS multidrain logic and stacked multidrain logic,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 47–56, Feb. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 47-56
    • Wu, C.-Y.1    Wang, J.-S.2    Tsai, M.-K.3
  • 17
    • 0019596788 scopus 로고
    • MULGA-An interactive symbolic layout system for the design of integrated circuits
    • July-Aug
    • N. H. E. Weste, “MULGA—An interactive symbolic layout system for the design of integrated circuits,” Bell Syst. Tech. J., vol. 60, pp. 823–858, July-Aug. 1981.
    • (1981) Bell Syst. Tech. J , vol.60 , pp. 823-858
    • Weste, N.H.E.1
  • 18
    • 0022135064 scopus 로고
    • FET scaling in domino CMOS gate
    • Oct
    • M. Shoji, “FET scaling in domino CMOS gate,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1067–1071, Oct. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 1067-1071
    • Shoji, M.1
  • 19
    • 0019049402 scopus 로고
    • A dense gate matrix layout method for MOS VLSI
    • A. D. Lopez and H.-F. S. Law, “A dense gate matrix layout method for MOS VLSI,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27
    • Lopez, A.D.1    Law, H.-F.S.2
  • 20
    • 0023576631 scopus 로고
    • MACS: A module assembly and compaction system
    • W. H. Crocker, R. Varadarajan, and C.-Y. Lo, “MACS: A module assembly and compaction system,” in Proc. ICCD, 1987, pp. 205–208.
    • (1987) Proc. ICCD , pp. 205-208
    • Crocker, W.H.1    Varadarajan, R.2    Lo, C.-Y.3
  • 21
    • 0022987951 scopus 로고
    • A high performance submicron CMOS process with self-aligned chan-stop and punch-through implant (Twin-Tub V)
    • M.-L. Chen et al., “A high performance submicron CMOS process with self-aligned chan-stop and punch-through implant (Twin-Tub V),” in IEDM Tech. Dig., 1986, 256–259.
    • (1986) IEDM Tech. Dig , pp. 256-259
    • Chen, M.-L.1
  • 22
    • 84870649151 scopus 로고
    • A high performance submicron Twin Tub V technology for custom VLSI applications
    • C. W. Leung et al., “A high performance submicron Twin Tub V technology for custom VLSI applications,” in Proc. CICC, 1988, pp. 25.1.1-25.1.4.
    • (1988) Proc. CICC , pp. 25.1.1-25.1.4
    • Leung, C.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.