The Effects of Gate Field on the Leakage Characteristics of Heavily Doped Junctions

IEEE Transactions on Electron Devices

Volumn 36, Issue 4, 1989, Pages 720-726

  Noble, Wendell P ^a   Voldman, Steven H ^a   Bryant, Andres ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL--RANDOM ACCESS; SEMICONDUCTOR DEVICES--JUNCTIONS;

DYNAMIC RANDOM ACCESS MEMORIES; GATE FIELD EFFECTS; HEAVILY DOPED JUNCTIONS; LEAKAGE CHARACTERISTICS; ULTRA LARGE SCALE INTEGRATION;

INTEGRATED CIRCUITS, VLSI;

EID: 0024646158     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.22477     Document Type: Article

References (11)

1. W. P. Noble and W.W.Walker, “Fundamental limitations on DRAM storage capacitors,” Circuits and Devices Mag., vol. 1, pp. 45-51, Jan. 1985.
2. S. H. Voldman, A. Bryant, and W. P. Noble, “Vertical storage trench gated diode leakage,” presented at the 45th Ann. Device Research Conf., Santa Barbara, CA, June 22-24, 1987, abstract IVB-4.
3. W. P. Noble, A. Bryant, and S. H. Voldman, “Parasitic leakage in DRAM trench storage capacitor vertical gated diodes,” in IEDM Tech. Dig., 1987, pp. 340-343.
4. A. S. Grove and D. J. Fitzgerald, “Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions,” Solid-State Electron., vol. 9, pp. 783-806, Aug. 1966.
5. R. F. Pierret, “The gate-controlled diode SO measurement and steady-state lateral current flow in deeply depleted MOS structures,” Solid-State Electron., vol. 17, pp. 1257-1269, Dec. 1974.
6. S. Banerjee, W. Richardson, J. Coleman, and A. Chatterjee, “A new three-terminal tunnel device,” IEEE Electron Device Lett., vol. EDL-8, pp. 347-349, Aug. 1987.
7. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” in IEDM Tech. Dig., 1987, pp. 718-721.
8. C. Chang and J. Lien, “Corner-field induced drain leakage in thin oxide MOSFETs,” in IEDM Tech. Dig., 1987, pp. 714-717.
9. N. C.-C. Lu, P. E. Cottrell, W. J. Craig, S. Dash, D. L. Critchlow, R. L. Mohler, B. J. Machesney, T. H. Ning, W. P. Noble, R. M. Parent, R. E. Scheuerlein, E. J. Sprogis, and L. M. Terman, “A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 627-634, Oct. 1986.
10. W. Shockley and W. T. Read, “Statistics of the recombinations of holes and electrons,” Phys. Rev., vol. 87, pp. 835-842, Sept. 1952.
11. J. Snel, “The doped Si/SiO2 interface,” Solid-State Electron., vol. 24, pp. 135-139, Feb. 1981.