An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance

IEEE Journal of Solid-State Circuits

Volumn 24, Issue 2, 1989, Pages 325-330

  Sun, Sam Yinshang ^a  

^a Semiconductor Product Division Rockwell International ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; PHASE LOCKED LOOPS;

DATA RECOVERY CIRCUIT; INPUT JITTER; PLL-BASED CLOCK; TRIPLE SAMPLER; VCO CENTER FREQUENCY;

ELECTRONIC CIRCUITS, TIMING;

EID: 0024645895     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.18592     Document Type: Article

References (4)

1. F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov. 1980.
2. K. J. Stern, N. S. Sooch, D. J. Knapp, and M. A. Nix, “A monolithic line interface circuit for T1 terminals,” in ISSCC Dig. Tech. Papers, 1987, pp. 292–293.
3. AT&T PUB 62411, “High capacity digital service interface specification,” 1985.
4. S. Y. Sun, “A PLL based clock and data recovery circuit with high input jitter tolerance,” in Proc. IEEE CICC, 1988, pp. 9.7.1-9.7.3.