Boolean Decomposition in Multilevel Logic Optimization

IEEE Journal of Solid-State Circuits

Volumn 24, Issue 2, 1989, Pages 399-408

  Devadas, Srinivas ^a   Wang, Albert R ^b   Newton, A Richard ^b   Sangiovanni Vincentelli, Alberto ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b Department of Electrical Engineering Computer Sciences of California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY--BOOLEAN FUNCTIONS; LOGIC DEVICES;

BOOLEAN DECOMPOSITION; BOOLEAN FACTORS; MULTILEVEL LOGIC; PROGRAMMABLE LOGIC ARRAY (PLA);

LOGIC CIRCUITS;

EID: 0024645638     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.18601     Document Type: Article

References (15)

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