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A Josephson Latch-Decoder
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Tokyo, Japan 1981 also Japan. J. Appl. Phys. Supplement 21–1
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A 64-bit Josephson memory circuit
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(Tokyo, Japan) 1982; also Japan. J. Appl. Phys. Supplement 22–1
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H. Suzuki, H. Shibayama, M. Kosugi, I. Hanyu, T. Igarashi, H. Hoko, T. Nakamura, S. Hasuo, and T. Yamaoka, “A 64-bit Josephson memory circuit”, 14th Conf. Solid State Devices (Tokyo, Japan) 1982; also Japan. J. Appl. Phys., vol. 22, Supplement 22–1, pp.601-602, 1983.
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3
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Characteristics of single flux quantum Josephson memory cells
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Dec.
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A decoder with OR gates for a Josephson high-density memory circuit
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T. Igarashi, H. Suzuki, S. Hasuo, and T. Yamaoka, “A decoder with OR gates for a Josephson high-density memory circuit”, IEEE J. Solid-State Circuits, vol. sc-22, pp. 85–91, Feb. 1987.
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A diagonal address generator for a Josephson memory circuit
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H. Suzuki and S. Hasuo, “A diagonal address generator for a Josephson memory circuit”, IEEE J. Solid-State Circuits, vol. sc-22, pp. 92–97, Feb. 1987.
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Suzuki, H.1
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A capacitively coupled SFQ Josephson memory cell
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H. Suzuki and S. Hasuo, “A capacitively coupled SFQ Josephson memory cell”, IEEE Trans. Electron-devices, vol. 35, pp. 1137–1143, July 1988.
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Suzuki, H.1
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7
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0021588062
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A 1-k bit Josephson RAM integrated with variable threshold cells
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Kobe
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I. Kurosawa, H. Nakagawa, A. Yagi, S. Takada, and H. Hayakawa, “A 1-k bit Josephson RAM integrated with variable threshold cells”, Extended Abstracts of 16th Conf. Solid State Devices and Materials (Kobe) (1984) pp. 619–622.
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280-PS PS 6-bit RCJL decoder using high-drivability AND unit circuit for a 1-kbit Josephson cache memory
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Oct.
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Y. Wada, S. Nagasawa, and I. Ishida, “280-PS PS 6-bit RCJL decoder using high-drivability AND unit circuit for a 1-kbit Josephson cache memory”, IEEE Solid-State Circuits, vol. sc-22, pp. 892–898, Oct. 1987.
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Wada, Y.1
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0021482437
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Josephson NOR decoder circuit for Josephson memory arrays
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T. Nakanishi and S. Fujita, “Josephson NOR decoder circuit for Josephson memory arrays”, Japan. J. Appl. Phys., vol. 23, no.8, pp.1002-1006, 1984.
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Current injection logic gate with four Josephson junctions
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Tokyo, Japan 1979; also Japan, J. Appl. Phys. Suppl. 19–1
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S. Takada, S. Kosaka, and H. Hayakawa, “Current injection logic gate with four Josephson junctions”, Proc. 11th Conf. Solid State Devices (Tokyo, Japan), 1979; also Japan, J. Appl. Phys., vol. 19, Suppl. 19–1, pp. 607–611, 1980.
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Takada, S.1
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Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctions
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Mar.
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S. Kotani, N. Fujimaki, T. Imamura, and S. Hasuo, “Ultrahigh-speed logic gate family with Nb/Al-AlO x /Nb Josephson junctions”, IEEE Trans. Electron-Devices, vol. ED-33, pp.379-384, Mar. 1986.
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A Subnanosecond Josephson tunneling memory cell with nondestructive readout
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Thin film of niobium for cryotron ground planes
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Joynson, R.E.1
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0018505245
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Model for a 15ns 16K RAM with Josephson junctions
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Aug.
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R. F. Broom, P. G. Gueret, W. Kotyczka, T. O. Mohr, A. Moser, A. Oosenbrug, and P. Wolf, “Model for a 15ns 16K RAM with Josephson junctions,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 690–699, Aug. 1979.
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High quality Nb/Al-AlOx/Nb Josephson junction
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S. Morohashi, F. Shinoki, A. Shoji, M. Aoyagi, and H. Hayakawa, “High quality Nb/Al-AlOx/Nb Josephson junction”, Appl. Phys. Lett., vol. 46, pp.1179-1181, Jun. 1985.
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Application of sputtered SiO2 insulator to Nb/AlOx/Nb Josephson junctions
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Oct.
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H. Hoko, T. Imamura, S. Ohara, and S. Hasuo, “Application of sputtered SiO 2 insulator to Nb/A1O x /Nb Josephson junctions”, J. Appl. Phys., vol. 62, pp. 3432–3435, Oct. 1987.
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