Memory Cell and Technology Issues for 64-and 256-Mbit One-Transistor Cell MOS DRAMs

Proceedings of the IEEE

Volumn 77, Issue 3, 1989, Pages 374-388

  Tasch, Al F ^a   Parker, Laureen H ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL--RANDOM ACCESS; INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICES, MOS;

256 MBIT MOS DRAM; 64 MBIT MOS DRAM; LEAKAGE CURRENT; MOS DRAM MEMORY CELL; SOFT ERROR RATE;

DATA STORAGE, SEMICONDUCTOR;

EID: 0024627370     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/5.24125     Document Type: Article

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