Calculation of Signal Delay in Integrated Interconnections

IEEE Transactions on Circuits and Systems

Volumn 36, Issue 2, 1989, Pages 272-276

  Harbour, Glez ^a   Drake, J M ^b  

^a Departmento de Eleltronica Universidad de Cantabria ^*

^b UNIVERSITY OF CANTABRIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORKS--EQUIVALENT CIRCUITS; INTEGRATED CIRCUITS--COMPUTER AIDED ANALYSIS; MATHEMATICAL TECHNIQUES--TRANSFER FUNCTIONS; MATHEMATICAL TRANSFORMATIONS--LAPLACE TRANSFORMS;

MULTITERMINAL EQUIVALENT NETWORK; RC NETWORKS; SIGNAL DELAY; TRANSIENT RESPONSE APPROXIMATION;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0024612479     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/31.20204     Document Type: Article

References (7)

1. J. Rubinstein, P. Penfield, and M.A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. Computer-Aided Design, vol. CAD-2, July 1983.
2. J.L. Wyatt, Jr., “Signal delay in RC mesh networks,” IEEE Trans. Circuits Syst., vol. CAS-32, May 1985.
3. Tzu-Mu Lin and C.A. Mead, “Signal delay in general RC networks,” IEEE Trans. Computer Aided Design, vol. CAD-3, Oct. 1984.
4. C.S. Lindquist, Active Network Design. Steward & Sons, 1977.
5. Z.A. Zukowski, “Relaxing bounds for linear RC mesh circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, Apr. 1986.
6. M. Glez. Harbour and J.M. Drake, “Calculation of multiterminal resistances in integrated circuits,” IEEE Trans. Circuits Syst., vol. CAS-33, Apr. 1986.
7. A.B. Bhattacharyya and M.L. Gupta, “Single-section lumped models for integrated circuit resistors,” Solid-State Electronics, vol. 16, pp. 1506–1509, 1973.