A Framework to Evaluate Technology and Device Design Enhancements for MOS Integrated Circuits

IEEE Journal of Solid-State Circuits

Volumn 24, Issue 1, 1989, Pages 118-127

  Sodini, Charles G ^a   Wong, S Simon ^b   Ko, Ping Keung ^c  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b Department of Obstetrics Gynecology   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; NOISE, SPURIOUS SIGNAL; SEMICONDUCTOR DEVICES, MOS;

APPLICATION SPECIFIC IC'S; CMOS STATIC CIRCUITS; DESIGN-INTENSIVE IC'S; FLICKER NOISE MODEL; MOS INTEGRATED CIRCUITS;

INTEGRATED CIRCUITS, VLSI;

EID: 0024612395     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.16311     Document Type: Article

References (13)

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