Effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1988, Pages 212-219

  Chen, Kueing Long ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES--STATIC ELECTRICITY; ELECTRONICS PACKAGING--STATIC ELECTRICITY; ELECTROSTATICS; SEMICONDUCTOR DEVICES, MOS--JUNCTIONS;

ELECTROSTATIC DISCHARGE (ESD); ESD FAILURE THRESHOLD; GATE POTENTIAL EFFECTS; INTERCONNECT PROCESS; NMOS TRANSISTORS; SNAPBACK VOLTAGE;

TRANSISTORS;

EID: 0024169423     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)