SOLO: A generator of efficient layouts from optimized MOS circuits schematics.

Proceedings - Design Automation Conference

Volumn , Issue , 1988, Pages 445-452

  Baltus, Donald G ^a   Allen, Jonathan ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORKS -- SCHEMATIC DIAGRAMS; SEMICONDUCTOR DEVICES, MOS; TRANSISTORS, BIPOLAR;

200 TRANSISTORS; EFFICIENT LAYOUTS; MODULE-SIZE CIRCUITS; MOS CIRCUITS; SIZED TRANSISTORS;

INTEGRATED CIRCUITS;

EID: 0024137453     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)