High packing density module generator for CMOS logic cells.

Proceedings - Design Automation Conference

Volumn , Issue , 1988, Pages 439-444

  Shiraishi, Yoichi ^a   Sakemi, Jun'ya ^a   Kutsuwada, Makoto ^a   Tsukizoe, Akira ^a   Satoh, Takashi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS -- COMPUTER AIDED DESIGN; SEMICONDUCTOR DEVICES, MOS;

CELL-PATTERN GENERATION; CMOS CIRCUIT DIAGRAM; CMOS LOGIC CELLS; INDUSTRIAL CHIPS; PACKING DENSITY;

LOGIC DESIGN;

EID: 0024133784     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)