Feature a Digital Signal Processor with Ieee Floating-Point Arithmetic

IEEE Micro

Volumn 8, Issue 6, 1988, Pages 49-67

  Sohie, Guy R L ^a   Kloker, Kevin L ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER GRAPHICS; COMPUTER SYSTEMS, DIGITAL--MULTIPROCESSING; DATA PROCESSING--NATURAL SCIENCES APPLICATIONS; IMAGE PROCESSING; SPECTRUM ANALYSIS;

FLOATING POINT ARITHMETIC; INSTRUCTION PIPELINING; PIPELINED ARCHITECTURE;

SIGNAL PROCESSING;

EID: 0024124854     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.16780     Document Type: Article

References (27)

1. ANSI/IEEE Standard 754-1985: IEEE Standard for Binary Floating-Point Arithmetic, IEEE Service Center, Piscataway, N.J., 1985.
2. K.L. Kloker, “The Motorola DSP56000 Digital Signal Processor,” IEEE Micro, vol. 6, No. 6, Dec. 1986, pp. 29–48.
3. J.M. Snell, “Professional realtime Signal Processor for Synthesis, Sampling, Mixing & Recording,” 83rd Convention Audio Eng. Soc, Oct. 1987, paper 2508 ‘M-4’.
4. T. Nishitani et al., “LSI Signal Processor Development for Communications Equipment,” Proc. IEEE Int'l Conf. Acoustics, Speech and Signal Processing, Apr. 1980, pp. 386–389.
5. S. Abiko et al., “Architecture and Applications of a 100-ns CMOS VLSI Digital Signal Processor,” Proc. IEEE Int'l Conf. ASSP, 1986, pp. 393–396.
6. J.P. Roesgen, “The ADSP-2100 DSP Microprocessor,” IEEE Micro, vol. 6, No. 6, Dec. 1986, pp. 49–59.
7. MC68881/MC68882 Floating-Point Coprocessor User's Manual, Publication No. MC68881UM/AD, Motorola, Inc., Austin, Texas, 1987.
8. MC88100 Technical Summary, Publication No. BR588/D, Motorola, Inc., 1988.
9. Weitek WTL3132/WTL3332 32 Bit Floating-Point Data Path, Weitek Corp., Sunnyvale, Calif., 1987.
10. J.R. Boddie et al., “The Architecture, Instruction Set and Development Support for the WE DSP32 Digital Signal Processor,” Proc. IEEE Int'l Conf. ASSP, paper 8.10, 1986, pp. 421–424.
11. R. Simar, Jr., et al., “A 40 MFLOPS Digital Signal Processor: The First Supercomputer on a Chip,” Proc. IEEE Int'l Conf. ASSP, paper 13.16, 1987, pp. 535–538.
12. T. Nishitani et al., “Advanced Single-Chip Signal Processor,” Proc. IEEE Int'l Conf. ASSP, paper 8.7, 1986, pp. 409–412.
13. Y. Mori et al., “Architecture of Highspeed 22-Bit Floating-Point Digital Signal Processor,” Proc. IEEE Int'l Conf. ASSP, paper 8.6, Chapter 22, 1986, pp. 405–408.
14. T. Kaneko et al., “A 50ns Floating-Point Signal Processor VLSI,” Proc. IEEE Int'l Conf. ASSP, paper 8.5, 1986, pp. 401–404.
15. A. Genusov et al., “A New, Highly Parallel, 32 Bit Floating-Point DSP Vector Signal Processor,” Proc. IEEE Int'l Conf. ASSP, paper V4.8, 1988, pp. 2116–2119.
16. K. L. Kloker, “The Architecture and Applications of the Motorola DSP56000 Digital Signal Processor Family,” Proc. IEEE Int'l Conf. ASSP, paper 13.13, 1987, pp. 523–526.
17. DSP56000/1 Digital Signal Processors User's Manual, Publication No. DSP56000UM/AD, Motorola, Inc., 1988.
18. Am29000 Streamlined Instruction Processor, Publication 09075, Advanced Micro Devices, Sunnyvale, Calif., 1987.
19. D.J. Lilja, “Reducing the Branch Penalty in Pipelined Processors,” Computer, vol. 21, No. 7, July 1988, pp. 47–55.
20. T. Diede et al., “The Titan Graphics Supercomputer Architecture,” Computer, vol. 21, No. 9, Sept. 1988, pp. 13–30.
21. F.J. Harris, “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform,” Proc. IEEE, vol. 66, No. 1, Jan. 1978, pp. 57–84.
22. M.J. Narasimha et al., “On the Computation of the Discrete Cosine Transform,” IEEE Trans. Communications, vol. COM-26, No. 6, June 1978, pp. 934–936.
23. H.S. Hou, “The Fast Hartley Transform Algorithm,” IEEE Trans. Computers, vol. C-36, No. 2, Feb. 1987, pp. 147–156.
24. H.V. Sorensen et al., “Real-Valued Fast Fourier Transform Algorithms,” IEEE Trans. ASSP, Vol. ASSP-35, No. 6, June 1987, pp. 849–863. ‘Corrections appear in IEEE Trans. Acoustics, Speech and Signal Processing, vol. ASSP-35, No. 9, Sept. 1987, p. 1353.’
25. K. Hwang, Computer Arithmetic, Principles, Architecture and Design, John Wiley and Sons, New York, 1979.
26. C.V. Ramamoorthy et al., “Some Properties of Iterative Square-Rooting Methods Using Highspeed Multiplication,” IEEE Trans. Computers, vol. C-21, No. 8, Aug. 1972.
27. R. Peterson et al., “Taking the Wraps off the 34020,” Byte, Sept. 1988, pp. 257–272.