Regular Correspondence On The Operation Of Cascode Gain Stages

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 6, 1988, Pages 1434-1437

  Abidi, Asad A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS--ANALYSIS;

BOOTSTRAPPED CIRCUITS; CASCADE CIRCUITS; CASCODE GAIN STAGES; FREQUENCY RESPONSE; INTRINSIC GAIN;

AMPLIFIERS;

EID: 0024124544     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.90043     Document Type: Article

References (9)

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2. H. Wallman, A. B. Macnee, and C. P. Gadsden, “A low noise amplifier,” Prot: IRE, vol. 36, pp. 700–708, June 1948.
3. T. C. Choi et al., “High frequency CMOS switched capacitor filters for communications applications,” IEEE J. Solid-state Circuits, vol. SC-18, pp. 652–664, Dec. 1983.
4. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1984.
5. J. Mc G. Sowerby, “Electronic circuitry,” Wireless World, vol. LIV, p. 249, July 1948.
6. P. R. Gray and R. G. Meyer, “MOS operational amplifier design—A tutorial overview,” IEEE J. Solid-state Circuits, vol. SC-17, pp. 969–982, Dec. 1982.
7. A. de la Plaza, “highfrequency switched-capacitor filter using unity-gain buffers,” IEEE J. Solid-state Circuits, vol. SC-21, pp. 470–477, June 1986.
8. L. E. Larson, K. W. Martin, and G. C. Temes, “GaAs switched capacitor circuits for video signal processing,” in ISSCC Dig. Tech. Papers ‘New York, NY’, 1987, pp. 40–41.
9. A. A. Abidi, “An analysis of bootstrapped gain enhancement techniques,” IEEE J. Solid-state Circuits, vol. SC-22, pp. 1200–1204, Dec. 1987. An Analog Trimming Circuit Based on a Floating-Gate Device EDUARD SÄCKINGER and WALTER GUGGENBÜHL, SENIOR MEMBER, IEEE Abstract—The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed. A simple trimming circuit based on this principle and delivering a differential current is described. Experimental results of a differential difference amplifier ‘DDA’ containing two such circuits are given. After trimming, an offset voltage of 10 μV and a nonlinearity of 0.1 percent are achieved.