High-Temperature Latchup Characteristics in VLSI CMOS Circuits

IEEE Transactions on Electron Devices

Volumn 35, Issue 12, 1988, Pages 2424-2426

  Shoucair, F S ^a  

^a BROWN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS; OSCILLATORS; SEMICONDUCTOR DEVICES, MOS;

CMOS CIRCUITS; CMOS INVERTERS; HOLDING CURRENTS; RING OSCILLATORS; TRIGGER CURRENTS;

INTEGRATED CIRCUITS, VLSI;

EID: 0024122580     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.8826     Document Type: Article

References (7)

1. J. G. Dooley and R. C. Jaeger, “Temperature dependence of latchup in CMOS circuits,” IEEE Electron Device Lett., vol. EDL-5, no. 2, pp. 41–43, Feb. 1984.
2. E. Sangiorgi, R. L. Johnston, M. R. Pinto, P. F. Bechtold, and W. Fichtner, “Temperature dependence of latch-up phenomena in scaled CMOS structures,” IEEE Electron Device Lett., vol. EDL-7, no. 1, pp. 28–31, Jan. 1986.
3. D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Ph.D. dissertation, Stanford Univ., Oct. 1980.
4. F. S. Shoucair, “Design considerations in high temperature analog CMOS integrated circuits,” IEEE Trans. Components, Hybrids, Manufact. Technol., vol. CHMT-9, no. 3, pp. 242–251, Sept. 1986.
5. F. S. Shoucair and J. M. Early, “High temperature diffusion leakage current dependent MOSFET small signal conductance,” IEEE Trans. Electron Devices, vol. ED-31, no. 12, pp. 1866–1872, Dec. 1984.
6. F. S. Shoucair, W. Hwang, and P. Jain, “Electrical characteristics of LSI silicon MOSFETs at very high temperatures, Part III: Modeling and circuit behavior,” IEEE Trans. Components, Hybrids, Manufact. Technol., vol. CHMT-7, no. 1, pp. 146–153, Mar. 1984.
7. N. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mobilities in silicon as a function of concentration and temperature,” IEEE Trans. Electron Devices, vol. ED-29, no. 2, pp. 292–295, Feb. 1982.