A Pipelined 13-bit, 250-ks/s, 5-V Analog-to-Digital Converter

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 6, 1988, Pages 1316-1323

  Sutarja, Sehat ^a   Gray, Paul R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS--DESIGN; SIGNAL PROCESSING--DIGITAL TECHNIQUES;

ANALOG TO DIGITAL CONVERTERS; CMOS INTEGRATED CIRCUITS; MONOTONICITY; PIPELINE PROCESSING; REFERENCE FEEDFORWARD ERROR CORRECTION;

DATA CONVERSION, ANALOG TO DIGITAL;

EID: 0024122159     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.90027     Document Type: Article

References (7)

1. S. Sutarja and P. R. Gray, “A 250 ks/s 13b pipelined A/D converter,” in ISSCC Dig. Tech. Papers ‘New York, NY’, 1988, pp. 228–229
2. S. H. Lewis and P. R. Gray, “A pipelined 5 MHz 9b ADC,” in ISSCC Dig. Tech. Papers ‘New York, NY’, Feb. 1987, pp. 210–211.
3. O. A. Horna, “A 150 Mbps A/D and D/A conversion system,” Comstat Tech. Rev., pp. 52–57, 1972.
4. H.-S. Lee, D. A. Hodges, and P. R. Gray, “A self-calibrating 15-bit A/D converter,” IEEE J. Solid-state Circuits, vol. SC-19, pp. 813–819, Dec. 1984.
5. C.-C. Shih, “Precision analog to digital and digital to analog conversion using reference recirculating algorithmic architectures,” Ph.D. Dissertation, Univ. of Calif., Berkeley, pp. 77-85, July 25, 1985.
6. S. Sutarja, “High-resolution pipelined analog-to-digital conversion,” Ph.D. Dissertation, Univ. of Calif., Berkeley, Apr. 1988.
7. L. C. Yiu, “Ratio-independent pipelined analog-to-digital conversion,” Ph.D. proposal, Univ. of Calif., Berkeley, Nov. 15, 1984.