Layout dependence of cmos latchup

IEEE Transactions on Electron Devices

Volumn 35, Issue 11 pt 2, 1988, Pages 1892-1901

  Menozzi, Roberto ^a   Selmi, Luca ^a   Sangiorgi, Enrico ^a   Crisenza, Giuseppe ^a   Cavioni, Tiziana ^a   Ricco, Bruno ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SEMICONDUCTOR DEVICES, MOS;

BUTTED CONTACTS; CIRCUIT LAYOUT; CMOS INTEGRATED CIRCUITS; GUARD RINGS; LATCHUP IMMUNITY;

INTEGRATED CIRCUITS;

EID: 0024108232     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.7402     Document Type: Article

References (9)

1. R. R. Troutman Latchup in CMOS Technology 1986 Kluwer Academic Boston
2. Y. Taur W. H. Chang R. H. Dennard Characterization and modelling of a latch-up free 1-μm CMOS technology IEDM Tech. Dig. 398 401 IEDM Tech. Dig. 1984
3. R. S. Payne W. R. Grant W. J. Bertram Elimination of latchup in bulk CMOS IEDM Tech. Dig. 248 251 IEDM Tech. Dig. 1980
4. R. R. Troutman Epitaxial layer enhancement of n-well guard rings for CMOS circuits IEEE Electron Device Lett. EDL-4 438 1983
5. E. Sangiorgi M. R. Pinto S. E. Swirhun R. W. Dutton Two-dimensional numerical analysis of latchup in a VLSI CMOS technology IEEE Trans. Electron Devices ED-32 2117 2130 1985
6. M. R. Pinto C. S. Rafferty R. W. Dutton PISCES-II: Poisson and continuity equation solver Sept. 1984 CA, Stanford Stanford Electron. Labs.
7. M. R. Pinto C. S. Rafferty H. R. Yeager R. W. Dutton PISCES-IIB: Supplementary report 1985 CA, Stanford Stanford Electron. Labs.
8. A. A. Vol'fson V. K. Subashiev Fundamental absorption edge of silicon heavily doped with donor or acceptor impurities Sov. Phys—Semicond. 1 327 332 Sept. 1967
9. J. W. Slotboom The pn product in silicon Solid-State Electron. 20 279 283 1977