Numerical Simulation of GaAs MESFET's on the Semi-insulating Substrate Compensated by Deep Traps

IEEE Transactions on Electron Devices

Volumn 35, Issue 11, 1988, Pages 1778-1785

  Horio, Kazushige ^a   Yanai, Hisayoshi ^a   Ikoma, Toshiaki ^b  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC SPACE CHARGE; ELECTRONS; SEMICONDUCTING GALLIUM ARSENIDE -- APPLICATIONS;

DEEP TRAPS; MESFET; NUMERICAL SIMULATION; SHORT CHANNEL EFFECT; SPACE CHARGE LAYER;

TRANSISTORS, FIELD EFFECT;

EID: 0024105622     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.7387     Document Type: Article

References (21)

1. T. Itoh and H. Yanai, “Stability of performance and interfacial problem in GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. ED-27, 27, pp. 1037–1045, 1980.
2. C. P. Lee, S. J. Lee, and B. M. Welch, “Carrier injection and backgating effect in GaAs MESFET’s,” IEEE Electron Device Lett., vol. EDL-3, pp. 97–98, 1982.
3. C. Kocot and C. A. Stolte, “Backgating in GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. ED-29, pp. 1059–1064, 1982.
4. S. Makram-Ebeid and P. Minondo, “The roles of the surface and the bulk of the semi-insulating substrate in low-frequency anomalies of GaAs integrated circuits,” IEEE Trans. Electron Devices, vol. ED-32, 32, pp. 632–642, 1985.
5. G. M. Martin, J. P. Farges, G. Jacob, J. P. Hallais, and G. Poiblaud, “Compensation mechanism in GaAs,” J. Appl. Phys., vol. 51, pp. 2840–2852, 1980.
6. K. Horio, T. Ikoma, and H. Yanai, “Effects of impurity compensation on I-V characteristics of n-i-n structures and backgating in GaAs integrated circuits,” in Proc. 3rd Conf. Semi-Insulating III-V Materials, (Kah-nee-ta, OR), pp. 354–363, 1984.
7. K. Horio, T. Ikoma, and H. Yanai, “Computer-aided analysis of GaAs n-i-n structures with a heavily compensated i-layer,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1242–1250, 1986.
8. K. Yamasaki, N. Kato, and M. Hirayama, “Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length,” IEEE Trans. Electron Devices, vol. ED-32, pp. 2420–2425, 1985.
9. W. L. Engl, H. K. Dirks, and B. Meinerzhagen, “Device modeling,” Proc. IEEE, vol. 71, pp. 10–33, 1983.
10. K. Yamaguchi, S. Asai, and H. Kodera, “Two-dimensional numerical analysis of stability criteria of GaAs FET’s,” IEEE Trans. Electron Devices, vol. ED-23, pp. 1283–1290, 1976.
11. T. Wada and J. Frey, “Physical basis of short-channel MESFET operation,” IEEE Trans. Electron Devices, vol. ED-26, pp. 476–490, 1979.
12. P. Bonjour, R. Castagné, J. F. Pône, J. P. Courat, G. Bert, G. Nuzillat, zillat, and M. Peltier, “Saturation mechanism in 1 µm gate FET with channel-substrate interface barrier,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1019–1024, 1980.
13. A. Yoshii, M. Tomizawa, and K. Yokoyama, “Accurate modeling for submicronmeter-gate Si and GaAs MESFET's using two-dimensional particle simulation,” IEEE Trans. Electron Devices, vol. ED-30, 30, pp. 1376–1380, 1983.
14. W. R. Curtice, “The performance of submicrometer gate length GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1693–1699, 1699, 1983.
15. M. F. Absaid and J. R. Hauser, “A comparative analysis of GaAs and Si ion-implanted MESFET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp. 908–912, 1986.
16. N. A. Mishima and K. Yamaguchi, “A two-dimensional numerical analysis of GaAs MESFET's with a p-buffer layer,” Trans. IEICE, vol. J70-C, pp. 631–636, 1987 (in Japanese).
17. K. Horio, H. Yanai, and T. Ikoma, “Numerical simulation of GaAs MESFET's with heavily compensated substrates,” in Proc. 5th Int. Conf. Numerical Analysis Semiconductor Devices Integrated Circuits (NASECODE V) (Dublin, Ireland), pp. 237–242, 1987.
18. D. E. Holmes, R. T. Chen, K. R. Elliot, C. G. Kirkpatrick, and P. W. Yu, “Compensation mechanism in liquid encapsulated Czochralski GaAs: Importance of melt stoichiometry,” IEEE Trans. Electron Devices, vol. ED-29, pp. 1045–1051, 1982.
19. H. K. Gummel, “Self-consistent iterative scheme for one-dimensional steady state transistor calculations,” IEEE Trans. Electron Devices, vol. ED-11, pp. 455–465, 1964.
20. D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a silicon Read diode oscillator,” IEEE Trans. Electron Devices, vol. ED-16, pp. 64–77, 1969.
21. W. Shockley and W. T. Read, “Statistics of the recombination of holes and electrons,” Phys. Rev., vol. 87, pp. 835–842, 1952.