A scheduling rule for job release in semiconductor fabrication

Operations Research Letters

Volumn 7, Issue 5, 1988, Pages 213-217

  Glassey, C Roger ^a   Resende, Mauricio G C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

production scheduling; simulation; stochastic models

Indexed keywords

JOB ANALYSIS; PRODUCTION CONTROL - COMPUTER SIMULATION; SEMICONDUCTOR DEVICE MANUFACTURE - PRODUCTION CONTROL;

JOB RELEASE POLICY; MACHINE FAILURE/REPAIR; STOCHASTIC MODELS;

INVENTORY CONTROL;

EID: 0024102409     PISSN: 01676377     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-6377(88)90033-8     Document Type: Article

References (13)

1. A state-of-the-art survey of dispatching rules for manufacturing job shop operations
2. Performance analysis techniques for IC manufacturing lines
3. New techniques for simulation modeling and analysis
4. Performmnce analysis modeling for manufacturing lines
5. Closed-loop job release control for VLSI circuit manufacturing
6. Search and Simulation Selection of a Job-Shop Sequencing Rule
7. The Fabrication of Microelectronic Circuits
8. A survey of scheduling rules
9. Computer simulation of semiconductor wafer fabrication
10. Shop floor scheduling of semiconductor wafer manufacturing