A Symmetric CMOS NOR Gate for High-Speed Applications

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1233-1236

  Johnson, Mark G ^a  

^a MIPS Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL -- DESIGN; LOGIC CIRCUITS -- DESIGN;

CMOS INTEGRATED CIRCUITS; HIGH SPEED LOGIC; NOR GATE;

LOGIC DEVICES;

EID: 0024092691     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5949     Document Type: Article

References (4)

1. J. Iwamura et al, “A high speed and low power CMOS/SOS multiplier-accumulator,” Microelectron. J., vol. 14, no. 6, pp. 49–57, 1983.
2. J. Iwamura, K. Suganuma, M. Kimura, and S. Taguchi, “A CMOS/SOS multiplier,” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 92–93.
3. S. Flannagan, “Synchronization reliability in CMOS technology,” IEEE J. Solidstate Circuits, vol. SC-20, pp. 880–882, Aug. 1985.
4. M. Nemes, “Driving large capacitances in MOS LSI systems,” IEEE J. Solidstate Circuits, vol. SC-19, pp. 159–161, Feb. 1984. A Hidden Surface and Shading Processor ‘HSSP’ with a Systolic Architecture TEIJI NISHIZAWA, TAKERU OHGI. HIROSHI KAMIYAMA. KAZUYASU NAGATOMI. AND KIYOSHI MAENOBU Abstract—A skewed systolic array architecture, which consists of 256 pixel processors ‘PP's’ in a chip, performs hidden surface elimination and smooth shading for three-dimensional ‘3-D’ graphics. The chip is based on a ScanLine Z-buffer algorithm. Segment tokens and sweep tokens flow through a unidirectional linear array of PP's, and the resulting video intensity data are output via a common bus. One PP has two 16-bit buffers ‘Z buffer, I buffer’ and a 16-bit arithmetic unit in its data path. Although each PP processes a token in four or five clocks, depending upon the shading mode, the token proceeds at a rate of one PP even clock. Therefore the intensity output rate is kept constant at the video frequency, i.e., 20 Mpixels per second. The chip is fabricated in 1.2-μm twin-rub CMOS technology. It contains 330K transistors on a 11.06X11.05-mm die, and operates with a 20-MHz single phase clock.