A 60-ns 16-Mbit CMOS DRAM with a Transposed Data-Line Structure

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1113-1119

  Aoki, Masakazu ^a   Nakagome, Yoshinobu ^a   Horiguchi, Masashi ^a   Tanaka, Hitoshi ^a   Ikenaga, Shin'ichi ^a   Etoh, Jun ^a   Kawamoto, Yoshifumi ^a   Kimura, Shintchiro ^a   Takeda, Eiji ^a   Sunami, Hideo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR -- STORAGE DEVICES; SEMICONDUCTOR DEVICES, MOS;

CMOS DRAM; DYNAMIC RANDOM ACCESS MEMORIES; HIGH DENSITY MEMORY ARRAYS; HIGH SPEED MEMORIES; TRANSPOSED DATA-LINE STRUCTURE;

DATA STORAGE, DIGITAL;

EID: 0024091832     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5932     Document Type: Article

References (12)

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3. S. Watanabe et al, “An experimental 16Mb DRAM chip with a 100 MHz serial read/write mode,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 248–249.
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11. M. Horiguchi et al, “Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM,” IEEE J. Solidstate Circuits, vol. 23, pp. 1128–1132, Oct. 1988.
12. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1983, ch. 8.