A 16-Mbit DRAM with a Relaxed Sense-Amplifier-Pitch Open-Bitline Architecture

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1104-1112

  Inoue, Michihiro ^a   Yamada, Toshio ^a   Kotani, Hisakazu ^a   Yamauchi, Hiroyuki ^a   Fujiwara, Atsushi ^a   Matsushima, Junko ^a   Akamatsu, Hironori ^a   Fukumoto, Masanori ^a   Kubota, Masafumi ^a   Nakao, Ichiro ^a   Aoi, Nobuo ^a   Fuse, Genshu ^a   Ogawa, Shin Ichi ^a   Odanaka, Shinji ^a   Ueno, Atsushi ^a   Yamamoto, Hiroshi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR -- STORAGE DEVICES; INTEGRATED CIRCUITS, DIGITAL -- METALLIZING; SEMICONDUCTOR DEVICES, MOS;

CMOS DRAM; DYNAMIC RANDOM ACCESS MEMORIES; HIGH DENSITY MEMORY CELL ARRAYS; OPEN-BIT-LINE ARCHITECTURE; SENSE AMPLIFIERS;

DATA STORAGE, DIGITAL;

EID: 0024091189     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5931     Document Type: Article

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