Improvement of Latchup Hardness by Geometry and Technology Tuning

IEEE Transactions on Electron Devices

Volumn 35, Issue 10, 1988, Pages 1609-1615

  Mazure, Carlos ^a   Takacs, Dezsoe ^a   Winnerl, Josef ^a   Reczek, Werner ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS -- DESIGN; SEMICONDUCTOR MATERIALS -- DOPING; TRANSISTORS, BIPOLAR;

CMOS TECHNOLOGIES; LATCHUP HARDNESS; PARASITIC BIPOLAR TRANSISTORS; SUBSTRATE TRIGGER CURRENTS;

SEMICONDUCTOR DEVICES, MOS;

EID: 0024090121     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.7361     Document Type: Article

References (9)

1. D. B. Estreich, Ph.D. dissertation, Stanford Univ. Stanford, CA, 1980
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3. R. D. Rung and H. Momose, “DC holding and dynamic triggering characteristics of bulk CMOS latchup,” IEEE Trans. Electron Devices, vol. ED-30, no. 12, pp. 1647–1655, 1983.
4. D. Takacs, J. Harter, E. P. Jacobs, C. Werner, U. Schwabe, J. Winnerl, and E. Lang, “Comparison of latch up in P- and N-well CMOS circuits,” in IEDM Tech. Dig., pp. 159–163, 1983.
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7. R. Troutman, “ latch up in CMOS Technology: The Problem and Its Cure. Norwell, MA: Kluwer Academic, 1986, ch. 5.
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9. H. C. Poon, A. K. Gummel, and D. L. Scharfetter, “High injection in epitaxial transistors,” IEEE Trans. Electron Devices, vol. ED-16, p. 455, 1969.