Dual-Operating-Voltage Scheme for a Single 5-V 16-Mbit DRAM

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1128-1132

  Horiguchi, Masashi ^a   Aoki, Masakazu ^a   Tanaka, Hitoshi ^a   Etoh, Jun ^a   Nakagome, Yoshinobu ^a   Ikenaga, Shin'ichi ^a   Kawamoto, Yoshifumi ^a   Itoh, Kiyoo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS, DIFFERENTIAL; DATA STORAGE, SEMICONDUCTOR -- STORAGE DEVICES; SEMICONDUCTOR DEVICES, MOS;

CMOS DRAM; DRAM SCALING; DUAL-OPERATING-VOLTAGE SCHEME; DYNAMIC RANDOM ACCESS MEMORIES; WORD-LINE BOOSTING;

DATA STORAGE, DIGITAL;

EID: 0024090005     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5934     Document Type: Article

References (7)

1. R. M. Parent et al, “A 4Mb DRAM with double-buffer static-column architecture.” in ISSCC Dig. Tech. Papers. Feb. 1987. pp. 14–15.
2. T. Mano et al, “Circuit technologies for 16Mb DRAMs,” in ISSCC Dig. Tech. Papers, Feb. 1987, pp. 22–23.
3. R. H. Dennard et al, “Design of ion-implanted MOSFET's with verv small physical dimensions,” IEEE J. Solidstate Circuits, vol. SC-5. pp. 256–268, Oct. 1974.
4. T. FuruYama et al “An experimental 4-Mbit CMOS DRAM,” IEEE J. Solidstate Circuits, vol. SC-21, pp. 605–611, Oct. 1986.
5. M. Sakamoto et al, “A 4-Mbit DRAM with half-internal-voltage bitline precharge.” IEEE J. Solidstate Circuits, vol. SC-21. pp. 612–617, Oct. 1986.
6. M. Aoki et al, “An experimental 16Mb DRAM with transposed data-line structure.” in ISSCC Dig. Tech. Papers. Feb. 1988. pp. 250–251.
7. K. Itoh et al, “An experimental 1Mb DRAM with on-chip voltage limiter,” in ISSCC Dig. Tech. Papers. Feb. 1984, pp. 282–283.