A 7.5-ns 32K×8 CMOS SRAM

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1054-1059

  Okuyama, Hiroaki ^a   Nakano, Takeshi ^a   Nishida, Shuichi ^a   Aono, Etsuro ^a   Satoh, Hisahiro ^a   Arita, Shigeru ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR -- STORAGE DEVICES; SEMICONDUCTOR DEVICES, MOS;

CMOS STATIC RAM; DATA OUTPUT RESET CIRCUIT; DOUBLE-ACTIVATED-PULSE CIRCUIT; HIGH SPEED MEMORIES; SELF-ALIGNED CONTACT TECHNOLOGY;

DATA STORAGE, DIGITAL;

EID: 0024088363     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5924     Document Type: Article

References (9)

1. K. L. Wang et al, “A 21-ns 32Kx8 CMOS static RAM with a selectively pumped p-well array,” IEEE J. Solidstate Circuits, vol. SC-22, pp. 704–711, Oct. 1987
2. T. Sakurai et al, “A low power 46-ns 256-kbit CMOS static RAM with dynamic double word line,” IEEE J. Solidstate Circuits, vol. SC-19,'pp. 578–585, Oct. 1984.
3. S. Yamamoto et al, “A 256K CMOS SRAM with variable impedance data-line loads,” IEEE J. Solidstate Circuits, vol. SC-20. pp. 924–928, Oct. 1985.
4. H. Shinohara et al, “A 45-ns 256K CMOS static RAM with a tri-level word line,” IEEE J. Solidstate Circuits, vol. SC-20, pp. 929–934, Oct. 1985.
5. S. Kayano et al, “25-ns 256KX1/64Kx4 CMOS SRAM's.” IEEE J. Solidstate Circuits, vol. SC-21, pp. 686–691, Oct. 1986.
6. S. T. Flannagan et al, “Two 13-ns 64K CMOS SRAM's with very' low active power and improved asynchronous circuit techniques.” IEEE J. Solidstate Circuits, vol. SC-21, pp. 692–703, Oct. 1986.
7. T. Komatsu et al, “A 35-ns 128Kx8 CMOS SRAM,” IEEE J. Solidstate Circuits, vol. SC-22, pp. 721–726, Oct. 1987.
8. T. Wada et al, “A 34-ns 1-Mbit CMOS SRAM using triple polv-silicon,” IEEE J. Solidstate Circuits, vol. SC-22, pp. 727–732, Oct. 1987.
9. O. Minato et al, “A 20ns 64K CMOS SRAM,” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 222–223.