Polarity Asymmetry of Oxides Grown on Polycrystalline Silicon

IEEE Transactions on Electron Devices

Volumn 35, Issue 7, 1988, Pages 1063-1070

  Lee, Jack C ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALS - GROWING; HEAT TREATMENT - ANNEALING; SEMICONDUCTING FILMS - ION IMPLANTATION; SEMICONDUCTING SILICON - DOPING;

IN SITU DOPED POLYSILICON; OXIDE THERMALLY GROWN ON POLYCRYSTALLINE SILICON; POLARITY ASYMMETRY; POLYOXIDE GROWTH;

OXIDES;

EID: 0024053861     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.3365     Document Type: Article

References (14)

1. D. DiMaria and D. Kerr, “Interface effects and high conductivity in oxides grown from polycrystalline silicon,” Appl. Phys. Lett., vol. 27, no. 9, p. 505, Nov. 1975.
2. R. Anderson and D. Kerr, “Evidence for surface asperity mechanism of conductivity in oxide grown on polycrystalline silicon,” J. Appl. Phys., vol. 48, no. 11, p. 4834, Nov. 1977.
3. E. Irene, E. Tiemy, and D. Dong, “Silicon oxidation studies: Morphological aspects of oxidation of polycrystalline silicon,” J. Electrochem. Soc., vol. 127, no. 3, p. 705, Mar. 1980.
4. H. Huff, R. Halvorson, T. Chiu, and D. Guterman, “Experimental observations on conduction through polysilicon oxide,” J. Electro chem. Soc., vol. 127, no. 11, p. 2482, Nov. 1980.
5. M. Sterheim, E. Kinsbron, J. Alspector, and P. Heimann, “Properties of thermal oxides grown on phosphorus in situ doped polysilicon,” J. Electrochem. Soc., vol. 130, no. 8, p. 1735, Aug. 1983.
6. L. Faraone, R. Vibronek, and J. McGinn, “Characterization of thermally oxidized n+ polycrystalline silicon,” IEEE Trans. Electron Devices, vol. ED-32, no. 3, p. 577, Mar. 1985.
7. S. Mori, T. Matsuda, T. Yanase, Y. Mikata, M. Sato, K. Shinada, K. Yoshikawa, and H. Nozawa, “Reliable CVD inter-poly dielectrics for advanced E&EEPROM,” VLSI Technol. Symp., pp. 16–17, May 1985.
8. Y. Mikata, S. Mori, K. Shinada, and T. Usami, “Low leakage current polysilicon oxide grown by two-step oxidation,” in 1985 IEEE/IRPS, p. 32. 1985.
9. P. Heimann, S. Murarka, and T. Sheng, “Electrical conduction and breakdown in oxides of polycrystalline silicon and their correlation with interface texture,” J. Appl. Phys., vol. 53, no. 9, p. 6240, Sept. 1982.
10. J. Drori, S. Jewell-Larsen, R. Klein, W. Owen, R. Simko, and W. Tchon, “A single 5-volt supply non-volatile static RAM,” IEEE Int. Solid State Circuits Conf. Tech. Dig., p. 198, 1984.
11. S. K. Lai, V. K. Dham, and D. Guterman, “Comparison and trends in today’s dominant E2 technologies,” in IEDM Tech. Dig., p. 580, Dec. 1986.
12. M. S. Liang and C. Hu, “Electron trapping in very thin thermal silicon dioxides,” in IEDM Tech. Dig., p. 396, Dec. 1981.
13. M. S. Liang, N. Ridjy, M. Cox, and S. Cagnina, “Charge trapping in dielectrics grown on polycrystalline silicon,” in Proc. Electrochem. Soc. Fall Meeting, p. 608, 1986.
14. I. C. Chen, S. Holland, and C. Hu, “Electrical breakdown in thin gate and tunneling oxides,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, p. 413, Feb. 1985.