Analysis of Logarithmic Number System Processors

IEEE Transactions on Circuits and Systems

Volumn 35, Issue 5, 1988, Pages 519-527

  Stouraitis, Thanos ^a   Taylor, Fred J ^b  

^a OHIO STATE UNIVERSITY   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

Author keywords

adaptive radix processor; error analysis; Logarithmic number system

Indexed keywords

INTEGRATED CIRCUITS, VLSI - APPLICATIONS;

24-BIT ADAPTIVE RADIX PROCESSOR (ARP); ADDITION/SUBTRACTION DATA PATH; LOGARITHMIC NUMBER SYSTEM (LNS) PROCESSOR; PREDICTIVE ERROR MODEL;

DATA PROCESSING;

EID: 0024014312     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/31.1779     Document Type: Article

References (26)

1. F. J. Taylor, Digital Filter Design Handbook. New York: Marcel-Dekker, 1983.
2. A. V. Oppenheim and R. W. Schafer, Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
3. B. Liu, “Effect of finite word length on the accuracy of digital filters—A review,” IEEE Trans. Circuit Theory, vol. CT-18, pp. 670–677, Nov. 1971.
4. B. Widrow, “Statistical analysis of amplitude-quantized sampled- data systems,” AIEE Trans. Appl. Ind., vol. 79, pp. 555–568, Jan. 1961.
5. J. Katzenelson, “On errors introduced by combined sampling and quantization,” IEEE Trans. Automat. Contr., vol. AC-7, pp. 58–68, Apr. 1962.
6. B. Gold and C. M. Rader, “Effects of quantization noise in digital filters,” in Proc. AFIPS 1966 Spring Joint Comput. Conf., vol. 8, 1986.
7. T. G. Mancuso and S. C. Lee, “Quantization, multiparameter sensitivity and round-off errors in digital filters,” in Proc. 6th Ann. All. Conf. Circuit Syst. Theory, pp. 621–629, Oct. 1968.
8. J. B. Knowles and E. M. Olcayto, “Coefficient accuracy and digital filter response,” IEEE Trans. Circuit Theory, vol. CT-15, pp. 31–41, Mar. 1968.
9. J. H. Wilkinson, Rounding Errors in Algebraic Processes. Englewood Cliffs, NJ: Prentice-Hall, 1963.
10. I. W. Sandberg, “Floating-point roundoff accumulation in digital filter realization,” Bell Syst. Tech. J., vol. 46, pp. 1775–1791, Oct. 1967.
11. T. Kaneko and B. Liu, “Roundoff error of floating-point digital filters,” in Proc. 6th Ann. All. Conf., pp. 219–229, 1968; also B. Liu and T. Kaneko, “Error analysis of digital filters realized with floating-point arithmetic,” Proc. IEEE, vol. 57, pp. 1735-1747, Oct. 1969.
12. A. Fettweis, “Properties of floating-point roundoff noise,” IEEE Trans. Acoust. Speech, Signal Processing, vol. ASSP-22, pp. 149–151, Apr. 1974.
13. T. Kurokawa, J. A. Payne, and S. C. Lee, “Error analysis of recursive digital filters implemented with logarithmic number systems,” IEEE Trans. Acoust. Speech, Signal Processing, vol. ASSP-28, Dec. 1980.
14. N. G. Kingsbury and P. J. W. Rayner, “Digital filtering using logarithmic arithmetic,” Electron. Lett., vol. 7, pp. 56–58, Feb. 1971.
15. S. C. Lee and A. D. Edgar, “The focus number system,” IEEE Trans. Comput., vol. C-26, pp. 1167–1177
16. S. C. Lee and A. D. Edgar, “Focus microcomputer number system,” in Microcomputer Design and Applications, S. C. Lee, Ed., New York: Academic, 1977.
17. E. E. Swartzlander, Jr. and A. G. Alexopoulos, “The sign/logarithm number system,” IEEE Trans. Comput., vol. C-24, pp. 1238–1242, Dec. 1975.
18. G. L. Sicuranza, “On effective implementation of 2-D digital filters using logarithmic number system,” IEEE Trans. Acoust. Speech, Signal Processing, vol. ASSP-31, Aug. 1983.
19. F. J. Taylor, “A hybrid floating-point logarithmic number system processor,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 92–95, Jan. 1985.
20. M. L. Frey and F. J. Taylor, “A table reduction technique for logarithmically architected digital filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-33, pp. 718–719, June 1985.
21. E. E. Swartzlander, Jr., D. V. Satish Chandra, H. Troy Nagle, Jr., and Scott A. Starks, “Sign/logarithm architecture for FFT implementation,” IEEE Trans. Comput., vol. C-32, June 1983.
22. T. Stouraitis, S. Natarajan, and F. Taylor, “A reconfiguration systolic primitive processor for signal processing” presented at the IEEE Int. Conf. on ASSP, Tampa, FL., March 1985.
23. J. H. Lang, C. A. Zukowski, R. O. Lamaire, and C. H. An, “Integrated-circuit logarithmic arithmetic units,” IEEE Trans. Comput., vol. C-34, May 1985.
24. F. J. Taylor, “A 20-bit VLSI arithmetic unit for digital signal processing in the logarithmic number system,” Signal Processing III: Theories and Applications, I. T. Young et al. (Eds.), New York: Elsevier Science, 1986.
25. T. Stouraitis, and F. Taylor, “Floating-point to logarithmic encoder error analysis,” IEEE Trans. Computers, vol. 37, May 1988.
26. A. Papoulis, Probability, Random Variables and Stochastic Processes. New York: McGraw-Hill, 1965.