Implementing Precise Interrupts in Pipelined Processors

IEEE Transactions on Computers

Volumn 37, Issue 5, 1988, Pages 562-573

  Smith, James E ^a   Pleszkun, Andrew R ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Performance simulation; pipelined computers; precise interrupts; process checkpointing; process recovery; virtual memory

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION;

PERFORMANCE DEGRADATION; PIPELINED PROCESSORS; PRECISE INTERRUPTS; PROCESS RECOVERY;

DATA PROCESSING;

EID: 0024013595     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.4607     Document Type: Article

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