Realizing Fault-Tolerant Interconnection Networks via Chaining

IEEE Transactions on Computers

Volumn 37, Issue 4, 1988, Pages 458-462

  Yew, Pen Chung ^b   Zhu, Chuan Qi ^b  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Multiprocessors; multistage interconnection networks; network fault tolerance; reliability analysis; routing schemes

Indexed keywords

COMPUTER NETWORKS - MEASUREMENTS; MATHEMATICAL TECHNIQUES - ALGORITHMS; RELIABILITY - ANALYSIS;

CHAINING; CONNECTING SWITCHING ELEMENTS; MEAN TIME TO FAIL (MTTF); MULTISTAGE INTERCONNECTION NETWORKS; SELF-ROUTING ALGORITHM;

COMPUTER SYSTEMS, DIGITAL;

EID: 0023997014     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.2191     Document Type: Article

References (15)

1. C.-L. Wu and T.-Y. Feng, Tutorial: Interconnection Networks for Parallel and Distributed Processing. IEEE Computer Science Press, 1984.
2. D. H. Lawrie, “Access and alignment of data in an array processor,’’ IEEE Trans. Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
3. C.-L. Wu and T.-Y. Feng, “On a class of multistage interconnection networks,” IEEE Trans. Comput., vol. C-29, pp. 694-702, Aug. 1980.
4. J. P. Shen and J. P. Hayes, “Fault tolerance of a class of connecting networks,” in Proc. 7th Annu. Symp. Comput. Architecture, 1980, pp. 61-71.
5. D. S. Parker and C. S. Raghavendra, “The gamma network: A multiprocessor interconnection network with redundant paths,” in Proc. 9th Annu. Symp. Comput. Architecture, Apr. 1982, pp. 73-80.
6. G. B. Adams III and H. J. Siegel, “The extra stage cube: A fault-tolerant interconnection network for supersystems,” IEEE Trans. Comput., vol. C-31, pp. 443-454, May 1982.
7. J. E. Lilienkamp, D. H. Lawrie, and P.-C. Yew, “A fault tolerant interconnection network using error correcting codes,” Dep. Comput. Sci. Rep. UIUCDCS-R-82-1094, Univ. Illinois Urbana-Champaign, June 1982.
8. K. Padmanabhan, “Fault tolerance and performance improvement in multiprocessor interconnection networks,” Ph.D. dissertation, Dep. Comput. Sci. Rep. UIUCDCS-R-84-1156, Univ. Illinois, Urbana-Champaign, May 1984.
9. C. S. Raghavendra and A. Varma, “INDRA: A class of interconnection networks with redundant paths,” in Proc. Real-Time Syst. Symp., Dec. 1984, pp. 153-164.
10. N.-F. Tzeng, P.-C. Yew, and C.-Q. Zhu, “A fault-tolerant scheme for multistage interconnection networks,” in Proc. 12th Int. Symp. Comput. Architecture, June 1985, pp. 368-375.
11. V. P. Kumar and S. M. Reddy, “Design and analysis of fault-tolerant multistage interconnection networks with low link complexity,” in Proc. 12th Int. Symp. Comput. Architecture, June 1985, pp. 376-386.
12. D. M. Dias and J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput., vol. C-30, pp. 273-282, Apr. 1981.
13. C.-T. A. Lea, “The load-sharing banyan network,” IEEE Trans. Comput., vol. C-35, pp. 1025-1034, Dec. 1986.
14. P. M. Lin, B. J. Leon, and T.-C. Huang, “A new algorithm for symbolic system reliability analysis,” IEEE Trans. Reliability, vol. R-25, pp. 2-15, Apr. 1976.
15. N.-F. Tzeng, “Fault-tolerant multiprocessor interconnection networks and their fault-diagnoses,” Ph.D. dissertation, Dep. Comput. Sci., Univ. Illinois, Urbana-Champaign, Aug. 1986.