Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 3, 1988, Pages 387-396

  Rose, Jonathan S ^a   Snelgrove, W Martin ^b   Vranesic, Zvonko G ^b  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; INTEGRATED CIRCUITS - LAYOUT;

PARALLEL ALGORITHM; SIMULATED ANNEALING; STANDARD CELL PLACEMENT;

INTEGRATED CIRCUITS, VLSI;

EID: 0023978575     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3172     Document Type: Article

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