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Volumn 7, Issue 2, 1988, Pages 160-167

SIMPL-2: (S/Mulated Profiles from the LayoutVersion 2)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER GRAPHICS - COLOR; COMPUTER PROGRAMMING - ALGORITHMS; DATA PROCESSING - DATA STRUCTURES; DATABASE SYSTEMS; ETCHING;

EID: 0023961236     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3145     Document Type: Article
Times cited : (8)

References (15)
  • 1
    • 0020949983 scopus 로고
    • SIMPL-I (SIMulated Profiles from the layoutversion 1)
    • presented at the Int. Electron Device Meeting, Dec.
    • M. A. Grimm, K. Lee. and A. R. Neureuther. “SIMPL-I (SIMulated Profiles from the layoutversion 1)”, presented at the Int. Electron Device Meeting, Dec. 1983.
    • (1983)
    • Grimm, M.A.1    Lee, K.2    Neureuther, A.R.3
  • 3
    • 84939364350 scopus 로고
    • KIC, A graphics editor for integrated circuits
    • Masters Rep., Dep. of Elect. Eng. and Comp. Sc., Univ. California, Berkeley, CA, June
    • K. H. Keller, “KIC, A graphics editor for integrated circuits”, Masters Rep., Dep. of Elect. Eng. and Comp. Sc., Univ. California, Berkeley, CA, June 1981.
    • (1981)
    • Keller, K.H.1
  • 5
    • 0022676727 scopus 로고
    • Topography simulation tools
    • Mar.
    • A. R. Neureuther, “Topography simulation tools”, Solid State Technology, pp. 71-75, Mar. 1986.
    • (1986) Solid State Technology , pp. 71-75
    • Neureuther, A.R.1
  • 6
    • 0018457024 scopus 로고
    • A general simulator for VLSI lithography and etching processes: Part 1Application to projection lithography
    • Apr.
    • W. G. Oldham, S. N. Nandgankar, A. R. Neureuther, and M. O'Toole, “A general simulator for VLSI lithography and etching processes: Part 1Application to projection lithography”, IEEE Trans. Electron Devices, vol. ED-26, pp. 717-722, Apr. 1979.
    • (1979) IEEE Trans. Electron Devices , vol.ED-26 , pp. 717-722
    • Oldham, W.G.1    Nandgankar, S.N.2    Neureuther, A.R.3    O'Toole, M.4
  • 7
    • 0019045498 scopus 로고
    • A general simulator for VLSI lithography and etching processes: Part IIApplication to deposition and etching
    • Aug.
    • W. G. Oldham, A. R. Neureuther, C. Sung, J. L. Reynolds, and S. N. Nandgaonkar, “A general simulator for VLSI lithography and etching processes: Part IIApplication to deposition and etching”, IEEE Trans. Electron Devices, vol. ED-27, pp. 1455-1459, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1455-1459
    • Oldham, W.G.1    Neureuther, A.R.2    Sung, C.3    Reynolds, J.L.4    Nandgaonkar, S.N.5
  • 8
    • 84939323190 scopus 로고
    • Program reference for KIC
    • Memo. UCB/ERL M83/62, Electron. Res. Lab., U.C. Berkeley, Oct.
    • G. C. Billingsley, “Program reference for KIC”, Memo. UCB/ERL M83/62, Electron. Res. Lab., U.C. Berkeley, Oct. 1983.
    • (1983)
    • Billingsley, G.C.1
  • 9
    • 0020091103 scopus 로고
    • Process design using two-dimensional process and device simulations
    • Feb.
    • D. Chin, M. R. Kump, H.-G. Lee, and R. W. Dutton, “Process design using two-dimensional process and device simulations”, IEEE Trans. Electron Devices, vol. ED-29, pp. 336-340, Feb. 1982.
    • (1982) IEEE Trans. Electron Devices , vol.ED-29 , pp. 336-340
    • Chin, D.1    Kump, M.R.2    Lee, H.G.3    Dutton, R.W.4
  • 10
    • 0019045647 scopus 로고
    • MINIMOS-A two-dimensional MOS transistor analyzer
    • Aug.
    • S. Selberherr, A. Schuetz, H. W. Poetzl, “MINIMOS-A two-dimensional MOS transistor analyzer”, IEEE Trans. Electron Devices, vol. ED-27, pp. 1540-1550, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1540-1550
    • Selberherr, S.1    Schuetz, A.2    Poetzl, H.W.3
  • 11
    • 0019045194 scopus 로고
    • Nonplanar VLSI device analysis using the solution of Poisson's equation
    • Aug.
    • J. A. Greenfield and R. W. Dutton. “Nonplanar VLSI device analysis using the solution of Poisson's equation”, IEEE Trans. Electron Devices, vol. ED-27, pp. 1520-1532. Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1520-1532
    • Greenfield, J.A.1    Dutton, R.W.2
  • 12
    • 0020716926 scopus 로고
    • OYSTER: A study of integrated circuits as three-dimensional structures
    • Mar.
    • G. M. Koppelman, and M. A. Wesley, “OYSTER: A study of integrated circuits as three-dimensional structures”, IBM J. Res. Develop., vol. 27, no. 2, Mar. 1983.
    • (1983) IBM J. Res. Develop. , vol.27 , Issue.2
    • Koppelman, G.M.1    Wesley, M.A.2
  • 13
  • 14
    • 1642621158 scopus 로고
    • General relationship for the thermal oxidation of silicon
    • Dec.
    • B. E. Deal and A. S. Grove, “General relationship for the thermal oxidation of silicon”, J. Appl. Phys., vol. 36, no. 12, Dec. 1965.
    • (1965) J. Appl. Phys. , vol.36 , Issue.12
    • Deal, B.E.1    Grove, A.S.2
  • 15
    • 0020180693 scopus 로고
    • A general solution method for two-dimensional nonplanar oxidation
    • Sept.
    • D. Chin, S. Y. Oh, and R. W. Dutton, “A general solution method for two-dimensional nonplanar oxidation”, IEEE Trans. Electron Devices, vol. ED-30, pp. 993-998, Sept. 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 993-998
    • Chin, D.1    Oh, S.Y.2    Dutton, R.W.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.