-
2
-
-
0021540210
-
Self-testing of embedded RAMs
-
Z. Sun and L. T. Wang, “Self-testing of embedded RAMs”, in Proc. Int. Test Conf, 1984, pp. 148-156.
-
(1984)
Proc. Int. Test Conf
, pp. 148-156
-
-
Sun, Z.1
Wang, L.T.2
-
3
-
-
0022184872
-
An efficient built-in self test scheme for functional test of embedded RAMs
-
M. Nicolaidis, “An efficient built-in self test scheme for functional test of embedded RAMs”, in Proc. Int. Test Conf., 1985, pp. 118-123.
-
(1985)
Proc. Int. Test Conf.
, pp. 118-123
-
-
Nicolaidis, M.1
-
4
-
-
0021548476
-
Random testing for stuck-at storage cells in an embedded memory
-
W. H. McAnney, P. H. Bardell, and V. P. Gupta, “Random testing for stuck-at storage cells in an embedded memory”, in Proc. Int. Test Conf, 1984, pp. 157-166.
-
(1984)
Proc. Int. Test Conf
, pp. 157-166
-
-
McAnney, W.H.1
Bardell, P.H.2
Gupta, V.P.3
-
5
-
-
0022329226
-
A methodology for testing content addressable memories
-
G. Giles and C. Hunter, “A methodology for testing content addressable memories”, in Proc. Int. Test Conf, 1985, pp. 471-474.
-
(1985)
Proc. Int. Test Conf
, pp. 471-474
-
-
Giles, G.1
Hunter, C.2
-
6
-
-
0022579064
-
The concept of a fault-tolerant and easily-testable associative memory
-
July
-
K. E. Grosspietsch, H. Huber, and A. Mueller, “The concept of a fault-tolerant and easily-testable associative memory”, in Proc. 16th Fault-Tolerant Computing Symp., July 1986, pp. 34-39.
-
(1986)
Proc. 16th Fault-Tolerant Computing Symp.
, pp. 34-39
-
-
Grosspietsch, K.E.1
Huber, H.2
Mueller, A.3
-
7
-
-
0015416866
-
Low-cost associative memory
-
J. L. Mundy, J. F. Burgess, R. E. Joynson, and C. Neugebauer, “Low-cost associative memory”, IEEE J. Solid-State Circuits, vol. SC-7, pp. 364-369, 1972.
-
(1972)
IEEE J. Solid-State Circuits
, vol.SC-7
, pp. 364-369
-
-
Mundy, J.L.1
Burgess, J.F.2
Joynson, R.E.3
Neugebauer, C.4
-
8
-
-
0017634911
-
An integrated test concept for switched-capacitor dynamic MOS RAM's
-
Dec.
-
T. C. Lo and M. R. Guidry, “An integrated test concept for switched-capacitor dynamic MOS RAM's”, IEEE J. Solid-State Circuits, vol. SC-12, pp. 693-703, Dec. 1977.
-
(1977)
IEEE J. Solid-State Circuits
, vol.SC-12
, pp. 693-703
-
-
Lo, T.C.1
Guidry, M.R.2
-
9
-
-
30244554943
-
High-density dynamic MOS memory devices
-
Apr.
-
P. K. Chatterjee, G. W. Tayor, A. F. Tasch, and H. S. Fu, “High-density dynamic MOS memory devices”, IEEE J. Solid-State Circuits, vol. SC-14, pp. 486-497, Apr. 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.SC-14
, pp. 486-497
-
-
Chatterjee, P.K.1
Tayor, G.W.2
Tasch, A.F.3
Fu, H.S.4
-
10
-
-
0019030541
-
Test procedures for a class of pattern sensitive faults in semiconductor random access memories
-
June
-
D. S. Suk and S. M. Reddy, “Test procedures for a class of pattern sensitive faults in semiconductor random access memories”, IEEE Trans. Comput., vol. C-29, pp. 419-429, June 1980.
-
(1980)
IEEE Trans. Comput.
, vol.C-29
, pp. 419-429
-
-
Suk, D.S.1
Reddy, S.M.2
-
12
-
-
0018997597
-
Testing memories for single-cell pattern-sensitive faults
-
Mar.
-
J. P. Hayes, “Testing memories for single-cell pattern-sensitive faults”, IEEE Trans. Comput., vol. C-29, pp. 249-254, Mar. 1980.
-
(1980)
IEEE Trans. Comput.
, vol.C-29
, pp. 249-254
-
-
Hayes, J.P.1
-
13
-
-
0023171952
-
Design and algorithms for parallel testing of random access and content addressable memories
-
July
-
P. Mazumder, J. H. Patel, and W. K. Fuchs, “Design and algorithms for parallel testing of random access and content addressable memories”, in Proc. Design Automat. Conf, vol. 24, July 1987, pp. 688-694.
-
(1987)
Proc. Design Automat. Conf
, vol.24
, pp. 688-694
-
-
Mazumder, P.1
Patel, J.H.2
Fuchs, W.K.3
-
14
-
-
84939343530
-
Testing and fault-tolerant aspects of high-density VLSI memory
-
Ph.D. thesis, Department of Electrical and Computer Engineering, University of Illinois, Aug.
-
P. Mazumder, “Testing and fault-tolerant aspects of high-density VLSI memory”, Ph.D. thesis, Department of Electrical and Computer Engineering, University of Illinois, Aug. 1987.
-
(1987)
-
-
Mazumder, P.1
-
15
-
-
0023524815
-
Planar decomposition for quadtree data structure
-
June
-
P. Mazumdar, “Planar decomposition for quadtree data structure”, Computer Vision, Graphics, and Image Processing, vol. 38, pp. 258-274, June 1987.
-
(1987)
Computer Vision, Graphics, and Image Processing
, vol.38
, pp. 258-274
-
-
Mazumdar, P.1
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