0.3-µm Advanced SAINT FET's Having Asymmetric n+-Layers for Ultra-High-Frequency GaAs MMIC's

IEEE Transactions on Electron Devices

Volumn 35, Issue 1, 1988, Pages 18-24

  Enoki, Takatomo ^a   Yamasaki, Kimiyoshi ^a   Osafune, Kazuo ^a   Ohwada, Kuniki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; INTEGRATED CIRCUITS, MONOLITHIC; LOGIC DEVICES - GATES;

ASYMMETRIC STRUCTURES; BURIED P-LAYER SELF-ALIGNED GATE (BP-SAINT) FET; PARASITIC GATE CAPACITANCES REDUCTION; SHORT-CHANNEL EFFECTS REDUCTION;

TRANSISTORS, FIELD EFFECT;

EID: 0023861914     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.2411     Document Type: Article

References (9)

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