Logic Design Verification via Test Generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 1, 1988, Pages 138-148

  Abadir, Magdy S ^a   Ferguson, Jack ^a   Kirkland, Thomas E ^a  

^a Microelectronics Computer Technology Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES, SYMBOLIC - ERROR DETECTION; LOGIC DEVICES - GATES;

FUNCTIONAL-LEVEL SPECIFICATION; GATE-LEVEL SPECIFICATION; SINGLE STRUCK-LINE FAULT DETECTION; TEST PATTERNS GENERATION;

LOGIC DESIGN;

EID: 0023829155     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3141     Document Type: Article

References (15)

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