Fault Tolerance Techniques for Systolic Arrays

Computer

Volumn 20, Issue 7, 1987, Pages 65-75

  Abraham, Jacob A ^a   Banerjee, Prithviraj ^a   Chen, Chien Yi ^a   Fuchs, W Kent ^a   Kuo, Sy Yen ^a   Narasimha Reddy, A L ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM-BASED FAULT TOLERANCE; CONCURRENT ERROR DETECTION (CED); SYSTOLIC ARRAYS; TIME REDUNDANCY;

CODES, SYMBOLIC - ERROR CORRECTION; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING - ALGORITHMS; INTEGRATED CIRCUITS, VLSI; REDUNDANCY;

COMPUTER SYSTEMS, DIGITAL;

EID: 0023383271     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.1987.1663621     Document Type: Article

References (0)