PARALLEL ALGORITHMS FOR CHIP PLACEMENT BY SIMULATED ANNEALING.

IBM Journal of Research and Development

Volumn 31, Issue 3, 1987, Pages 391-402

  Darema, F ^a   Kirkpatrick, S ^a   Norton, V A ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; INTEGRATED CIRCUITS - COMPUTER AIDED DESIGN;

CHAOTIC APPROACHES; CHIP PLACEMET; CIRCUIT PLACEMENT; PARALLEL ALGORITHMS; SIMULATED ANNEALING;

COMPUTER SYSTEMS, DIGITAL;

EID: 0023349607     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.313.0391     Document Type: Article

References (9)