A Two-Dimensional Etching Profile Simulator: ESPRIT

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 3, 1987, Pages 417-422

  Yamamoto, Shuichi ^a   Kure, Tokuo ^a   Ohgo, Masanori ^a   Matsuzama, Toshiharu ^a   Tachi, Shin'ichi ^a   Sunami, Hideo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION;

DESIGN PATTERNING PROCESS; MULTILAYERS; TWO-DIMENSIONAL ETCHING PROFILE SIMULATOR (ESPRIT);

INTEGRATED CIRCUITS, LSI;

EID: 0023347298     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270287     Document Type: Article

References (12)

1. H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S. Asai, “A corrugated capacitor cell (CCC) for megabit dynamic MOS memories,” IEEE IEDM Tech. Dig., pp. 806–808, Dec. 1982.
2. R. Rung, “Trench isolation prospects for application in CMOS VLSI,” IEEE IEDM Tech. Dig., pp. 574–577, Dec. 1984.
3. Y. Sakai, T. Hayashida, R. Nagai, S. Yamamoto, T. Yamanaka, T. Kure, and O. Minato, “A buried Giga-ohm resistor (BGR) load static RAM cell., VLSI Symp. Tech. Dig., 6–7, May 1984.
4. J. Colinge and E. Demoulin, “ST-CMOS (Stacked transistor CMOS): A double-poly-NMOS-compatible CMOS technology,” IEEE IEDM Tech. Dig., pp. 557–560, Dec. 1981.
5. M. Ohkura, K. Kusukawa. H. Sunami, T. Hayashida, and T. Tokuyama, “A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS),” IEEE IEDM Tech. Dig., pp. 718–721, Dec. 1985.
6. W. Oldham, S. Nandgaonker, A. Neureuther, and M. O'Toole, “A general simulator for VLSI lithography and etching processes: Part I—Applications to projection lithography,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 717–722, Apr. 1979.
7. W. Oldham. A. Neureuther, C. Sung, J. Reynolds, and S. Nand-gaonker, “A general simulator for VLSI lithography and etching processes: Part II—Applications to deposition and etching,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1455–1459, Aug. 1980.
8. T. Arikado, K. Horioka, M. Sekine. H. Okano, and Y. Horiike, “Single crystalline silicon etching characteristics and profile simulation,” in Proc. Symp. Dry Process, Nov. 1985, pp. 114–119.
9. R. Jewett, “A string model etchng algorithm,” Memo. No. UCB/ ERL. M79/68, Electronics Res. Lab., Univ. of California, Berkeley, Oct. 1979.
10. R. Jewett, P. Hagouel, A. Neureuther, and T. Van Duzer, “Line-profile profile resist development simulation techniques,” Polymer Eng. Sci., vol. 17, no. 6, pp. 381–384, June, 1977.
11. S. Isomae, S. Yamamoto, S. Aoki, and A. Yajima, “Oxidation-induced stress in a LOCOS structure,” IEEE Electron Devices Lett., vol. EDL-7 no. 6. pp. 368–370. June 1986.
12. S. Nakajima, K. Miura, K. Minegishi, and T. Morie, “An isolation-merged merged vertical capacitor cell for large capacity DRAM,” IEEE IEDM Tech. Dig., pp. 240–243. Dec. 1984.