An Analytic Model of Holding Voltage for Latch-Up in Epitaxial CMOS

IEEE Electron Device Letters

Volumn 8, Issue 4, 1987, Pages 157-159

  Seitchik, Jerold A ^a   Chatterjee, A ^a   Yang, Ping ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC MEASUREMENTS - VOLTAGE;

EPITAXIAL CMOS; HOLDING VOLTAGE; LATCH-UP;

SEMICONDUCTOR DEVICES, MOS;

EID: 0023331957     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26586     Document Type: Article

References (18)

1. G. J. Hu and R. H. Bruce, “A CMOS structure with high latchup holding voltage,” IEEE Electron Device Lett., vol. EDL-5, p. 211, 1984.
2. F. S. Lai et al., “A highly latchup-immune 1μm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2,” in IEDM Tech. Dig., 1985, p. 513.
3. Y. Niitsu et al., “Latchup-free CMOS structure using shallow trench isolation.” in IEDM Tech. Dig., 1985, p. 509.
4. E. Sangiorgi, R. L. Johnston, M. R. Pinto, P. F. Bechtold, and W. Fichtner, ‘‘Temperature dependence of latch-up phenomena in scaled CMOS structures.” IEEE Electron Device Lett., vol. EDL-7, p. 28, 1986.
5. A. G. Lewis, R. A. Martin, T. Y. Huang, J. Y. Chen, and R. H. Bruce, “Scaling CMOS technologies with constant latch-up immunity,” in 1986 Symp. VLSI Technol., 1986, p. 23.
6. H. P. Zappe, R. K. Gupta, K. W. Terrill, and C. Hu, “Floating well CMOS and latchup,” in IEDM Tech. Dig., 1985, p. 517.
7. Y. Taur, W. H. Chang, and R. H. Dennard, “Characterization and modeling of a latchup-free CMOS technology,” in IEDM Tech. Dig., 1984, p. 398.
8. S. Swirhun, E. Sangiorgi, A. Weeks, R. M. Swanson, K. C. Saraswat, and R. W. Dutton, “Latchup free CMOS using guarded Schottky barrier PMOS,” in IEDM Tech. Dig., 1984, p. 402.
9. J. E. Hall, J. A. Seitchik, L. A. Arledge, P. Yang, and P. K. Fung, “Analysis of latchup susceptibility in CMOS circuits.” in IEDM Tech. Dig., 1984, p. 292.
10. G. Krieger, ‘‘A new technique to accurately determine latch-up holding conditions using light excitation,” IEEE Electron Device Lett., vol. EDL-7, 1986, p. 232.
11. D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits.” Ph.D. dissertation. Stanford Univ., Stanford, CA. 1980.
12. J. E. Hall, J. A. Seitchik, L. A. Arledge, and P. Yang, “An improved circuit model for CMOS latchup,” IEEE Electron Device Lett., vol. EDL-6, p. 320. 1985.
13. M. R. Pinto, C. S. Rafferty, and R. W. Dutton, PISCES-II User’s Manual, Stanford Univ., Stanford, CA, 1984.
14. A. Herlet and K. Raithel, “Forward characteristics of thyristors in the fired state,” Solid-State Electron., vol. 9, p. 1089, 1966.
15. A. Chatterjee, J. A. Seitchik, and P. Yang, in preparation.
16. J. R. A. Beale and J. A. G. Slatter, “The equivalent circuit of a transistor with a lightly doped collector operating in saturation,” Solid-State Electron., vol. 11, p. 241, 1968.
17. A. Herlet, “The forward characteristic of silicon power rectifiers at high current densities,” Solid-State Electron., vol. 11, p. 717, 1968.
18. A. Chatterjee, J. A. Seitchik, and P. Yang, “A simple holding voltage analysis for latchup in epitaxial CMOS,” in 1986 Symp. VLSI Technol., 1986, p. 25.