Three-Dimensional Distribution of CMOS Latch-Up Current

IEEE Electron Device Letters

Volumn 8, Issue 4, 1987, Pages 154-156

  Sangiorgi, Enrico ^a   Ricco, Bruno ^a   Selmi, L ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS - MEASUREMENTS;

3-D CURRENT DISTRIBUTION; CMOS LATCH-UP CURRENT;

ELECTRIC MEASUREMENTS;

EID: 0023330770     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/EDL.1987.26585     Document Type: Article

References (6)

1. G. J. Hu, “A better understanding of CMOS latch-up,” IEEE Trans. Electron Devices, vol. ED-31, p. 62, 1984.
2. G. J. Hu and R. H. Bruce, “A CMOS structure with high latch-up holding voltage,” IEEE Electron Device Lett., vol. EDL-5, p. 211, 1984.
3. S. Swirhun, E. Sangiorgi, A. Weeks, R. M. Swanson, K. C. Saraswat, and R. W. Dutton, “Latch-up free CMOS using guarded Schottky barrier PMOS,” in IEDM Tech. Dig., 1984, p. 402.
4. E. Sangiorgi, M. R. Pinto, S. E. Swirhun, and R. W. Dutton, “Two-dimensional numerical analysis of latch-up in a VLSI CMOS technology,” IEEE Trans. Electron Devices, vol. ED-32, pp. 2117–2130, 1985.
5. M. R. Pinto, C. S. Rafferty, and R. W. Dutton, “PISCES-II: Poisson and continuity equation solver,” Stanford Electron. Labs., Stanford, CA, Rep., Sept. 1984.
6. S. B. Ghandhy, Semiconductor Power Devices. New York: Wiley, 1977.